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Machine learning algorithms, such
as those for image based search, face recognition, multi-category
classification, and scene analysis, are being developed that will
fundamentally alter the way individuals and organizations live, work, and
interact with each other. However their computational complexity still
challenges the state-of-the-art computing platforms, especially when the
application of interest is tightly constrained by the requirements of low power,
high throughput, small latency, etc.
In recent
years, there have been enormous advances in implementing machine learning
algorithms with application-specific hardware (e.g., FPGA, ASIC, etc.).
There is a timely need to map the latest learning algorithms to physical
hardware, in order to achieve orders of magnitude improvement in
performance, energy efficiency and compactness. Recent progress in
computational neurosciences and nanoelectronic technology, such as
resistive memory devices, will further help shed light on future
hardware-software platforms for learning on-a-chip.
The
overarching goal of this workshop is to explore the potential of on-chip
machine learning, to reveal emerging algorithms and design needs, and to
promote novel applications for learning. It aims to establish a forum to
discuss the current practices, as well as future research needs in the
fields below.
Key Topics
Synaptic plasticity and neuron motifs of learning dynamics
Computation models of cortical activities
Sparse learning, feature extraction and personalization
Deep learning with high speed and high power efficiency
Hardware acceleration for machine learning
Hardware emulation of brain
Nanoelectronic devices and architectures for neuro-computing
Applications of learning on a smart mobile platform
8:15am – 8:30am
Introduction and Opening Remarks
8:30am – 9:15am
Keynote talk 1
Naresh Shanbhag (UIUC):
Designing AI Systems at the Edge - Shannon-inspired Deep In-memory Architectures
9:15am – 10:00am
Keynote talk 2
Yangqing Jia (Facebook):
10:00am – 10:15am
Coffee Break
10:15am – 11:30am
Session 1: Hardware Acceleration of Machine Learning, Chair: Wujie Wen (Florida International University)
Shouyi Yin (Tsinghua University):
Towards Deploying AI Everywhere: Highly Energy Efficient Reconfigurable Neural Network Processor for Deep Learning Applications
Lingchuan Meng (ARM):
Hardware-Efficient Winograd Convolution via Integer Arithmetic
Yanzhi Wang (Northeastern University):
Towards 1,000X Model Compression and 10,000X Computation Reduction in Deep Neural Networks
11:30am – 12:45pm
Lunch
12:45am – 1:30pm
Keynote talk 3
Wen-Chung Chen (AMD): Machine Learning for Physical Design
1:30pm – 2:45pm
Session 2: Intelligent Systems and Applications, Chair: Frank Liu (IBM)
Jaeyoun Kim (Google):
Google Lens Suggestions: Real-time AI in the Viewfinder
Jishen Zhao (UCSD):
Software and Hardware Co-design for Scalable and Energy-efficient Neural Network Training with Processing-in-Memory
Xiang Chen (George Mason University):
Adversarial Examples, Threats or Promises: Case Studies on Mobile Application
2:45pm – 4:00pm
Session 3: Neuromorphic Computing, Chair: Sean Li (Qualcomm)
Gregory Chen (Intel):
Digital Spiking Neural Networks with On-chip Spike Timing Dependent Plasticity
Wei Lu (University of Michigan):
RRAM Fabric for Neuromorphic and In-memory Computing Applications
Gert Cauwenberghs (UCSD):
Memory-Efficient Neuromorphic Learning and Inference
4:00pm – 5:00pm
Session 4: Poster Session
Student poster presentations
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