Yu (Kevin) Cao

Professor, Electrical Engineering
Affiliated Professor, Computer Science and Engineering

B.S. (1996) Peking University, China
M.A. (1999) University of California, Berkeley
Ph.D. (2002) University of California, Berkeley

Prof. Cao was a recipient of the the 2012 Best Paper Award at ISVLSI, the 2010, 2012, 2013, 2015 and 2016 Teaching Excellence Award, Schools of Engineering, ASU, the 2009 ACM SIGDA Outstanding New Faculty Award, the 2009 Promotion and Tenure Faculty Exemplar, ASU, the 2008 Chunhui Award for Outstanding Oversea Chinense Scholars, the 2007 Best Paper Award at ISLPED, the 2006 NSF CAREER Award, the 2006 and 2007 IBM Faculty Award, the 2004 Best Paper Award at ISQED, and the 2000 Beatrice Winner Award at ISSCC. He was elevated to IEEE Fellow in 2017, for development of predictive technology models for reliable circuit and system integration. He currently serves on the technical program committee of many design automation and circuit design conferences.

Email: ycao AT asu DOT edu


Xiaocong Du

(Joined NIMO Group in 2016)

Research: Neuromorphic design; neural-inspired learning.

Email: xiaocong DOT du AT asu DOT edu

Srivatsava Gorthy

(Joined NIMO Group in 2016)

Research: Neural-inspired information analytics; neuromorphic design.

Email: sgorthy2 AT asu DOT edu

Abinash Mohanty

(Joined NIMO Group in 2013)

Research: Neuromorphic design for learning; stochastic design with extremely scaled CMOS.

Email: amohant4 AT asu DOT edu

Devyani Patra

(Joined NIMO Group in 2016)

Research: Reliability modeling, characterization and accelerated aging test.

Email: dpatra1 AT asu DOT edu

Zihan Xu

(Joined NIMO Group in 2011)

Research: Compact modeling of emerging memory devices; cross-layer design solutions for resilience.

Email: zihanxu AT asu DOT edu

Visiting Scholar

Zhiming Yang

(Joined NIMO Group in 2016)

Research: CMOS device and circuit reliability; failure prediction.

Email: zyang120 AT asu DOT edu

  • Ankita Bansal (MS, June 2016, Thesis "Reliability issues and design solutions in advanced CMOS design," now with Intel)
  • Naveen Suda (Ph.D., December 2015, Thesis "Reconfigurable architectures and systems for IoT applications," now with ARM)
  • Ketul Sutaria (Ph.D., November 2014, Thesis "Modeling and simulation tools for aging effects in scaled CMOS design," now with Intel)
  • Pei An (MS, November 2013, Thesis "Reliable arithmetic circuit design inspired by SN P systems," now with Supertex)
  • Yao Ma (Visiting Scholar, Sichuan University, China, September 2012 - August 2013)
  • Venkatesa Sarma Ravi (MS, February 2013, Thesis "Statistical characterization and decomposition of SRAM cell variability and aging," now with Samsung)
  • Anupama Subramaniam (Ph.D., November 2012, Thesis "Efficient circuit analysis under multiple input switching," now with Intel)
  • Jyothi Velamala (Ph.D., November 2012, Thesis "Compact modeling and simulation for digital circuit aging," now with Intel)
  • Cheng Xu (MS, November 2012, Thesis "Programmable analog device array (PANDA): a methodology for transistor-level analog emulation," now with Microchip)
  • Saurabh Sinha (Ph.D., November 2011, Thesis "Neuromorphic controller for low power systems: from devices to circuits," now with ARM)
  • Yun Ye (Ph.D., April 2011, Thesis "Modeling and simulation fo variations in nano-CMOS design," now with Proplus)
  • Run Zheng (MS, April 2011, Thesis "Aging predictive models and simulation methods for analog and mixed-signal circuits", now with Loongson)
  • Chi-Chao Wang (Ph.D., March 2011, Thesis "Predictive modeling for extremely scaled CMOS and post-silicon devices," now with Intel)
  • Jia Ni (MS, May 2010, Thesis "Rigorous extraction of Vth variation in SRAM cell transistors," now with Bloomberg L. P.)
  • Min Chen (Ph.D., May 2010, Thesis "Design for reliability: from silicon characterization, model calibration, to efficient simulation," now with Texas Instruments)
  • Varsha Balakrishnan (MS, Nov 2009, Thesis "Circuit aging simulation for digital and analog circuits," now with Global Foudries)
  • Wei Zhao (Ph.D., March 2009, Thesis "Predictive technology modeling for scaled CMOS design," now with Qualcomm)
  • Wenping Wang (Ph.D., June 2008, Thesis "Circuit aging in scaled CMOS design: modeling, simulation, and prediction," now with Qualcomm)
  • Dinesh Ganesan (MS, Dec 2007, Thesis "Finite point gate model," now with Freescale)
  • Asha Balijepalli (Ph.D., Dec 2007, Thesis "Compact modeling and applications of a PD SOI MESFET," now with Global Foundries)
  • Ritu Singhal (MS, Sept 2007, Thesis "Compact modeling of non-rectangular gate effect," now with Intel)
  • Rakesh Vattikonda (MS, July 2007, Thesis "Predictive modeling of NBTI effect," now with Qualcomm)
  • Tarun Sairam (MS, July 2006, Thesis "Low-power digital design with FinFET technology," now with Sun)