Publications

    2016

  1. C. Yang, M. Mao, Y. Cao, C. Chakrabarti, “Cost-effective design solutions for enhancing PRAM reliability and performance,” to be published in IEEE Transactions on Multi-Scale Computing Systems.

  2. P.-Y. Chen, J. Seo, Y. Cao, S. Yu, “Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing,” International Conference on Computer Aided Design, a15.1-6, 2016.

  3. Y. Ma, N. Suda, J. Seo, Y. Cao, S. Vrudhula, “Scalable and modularized RTL compilation of convolutional neural networks onto FPGA,” International Conference on Field-Programmable Logic and Applications, S5b.1-8, 2016.

  4. M. Mao, Y. Cao, S. Yu, C. Chakrabarti, “Optimizing latency, energy, and reliability of 1T1R ReRAM through cross-layer techniques,” to be published in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Special Issue on Emerging Memory Technology, Architecture and Applications, vol. 6, no. 3, pp. 352-363, September, 2016.

  5. M. Tu, V. Berisha, Y. Cao, J. Seo, “Reducing the model order of deep neural networks using information theory,” IEEE Computer Society Annual Symposium on VLSI, pp. 93-98, arXiv 1605.04859, 2016. [invited]

  6. S. Yin, Y. Ma, Y. Liu, C. Bae, S. Kim, S. Vrudhula, J. He, Y. Cao, J. Seo, “Low-power ECG biometric authentication for wearable systems featuring sparse memory compression,” ICML 2016 Workshop on On-device Intelligence, pp. 1-5, 2016.

  7. A. Shrivastava, P. K. Deo, Z. Xu, P.-Y. Chen, S. Yu, Y. Cao, C. Chakrabarti, “Design of a reliable RRAM-based PUF for compact hardware security primitives,” International Symposium on Circuits and Systems, pp. 2326-2329, 2016.

  8. A. Mohanty, N. Suda, M. Kim, S. Vrudhula, J. Seo, Y. Cao, “High-performance face detection with CPU-FPGA acceleration,” International Symposium on Circuits and Systems, pp. 117-120, 2016. [invited]

  9. Z. Xu, P.-Y. Chen, J. Seo, S. Yu, Y. Cao, “Hardware-efficient learning with feedforward inhibition,” International Nanoelectronics Conference, W5-1, pp. 1-2, 2016. [invited]

  10. M. Tu, V. Berisha, M. Woolf, J. Seo, Y. Cao, “Ranking the parameters of deep neural networks using the Fisher information,” International Conference on Acoustics, Speech and Signal Processing, pp. 2647-2651, 2016.

  11. Y. Cao, S. Yu, Y. Wang, P.-Y. Chen, L. Xia, H. Yang, “Neuromorphic computing with resistive synaptic arrays: devices, circuits and systems,” International Symposium on Quality Electronic Design, 2016. [invited]

  12. L. Xia, P.-Y. Chen, Y. Cao, S. Yu, Y. Wang, H. Yang, “MNSIM: Simulation platform for memristor-based neuromorphic computing system,” Design, Automation & Test in Europe, pp. 469-474, 2016.

  13. N. Suda, V. Chandra, G. Dasika, A. Mohanty, Y. Ma, S. Vrudhula, J. Seo, Y. Cao, “Throughput-optimal OpenCL-based FPGA accelerator for large-scale convolutional neural networks,” International Symposium on Field-Programmable Gate Arrays, pp. 16-25, 2016.

  14. L. Xia, P. Gu, B. Li, T. Tang, X. Yin, W. Huang, S. Yu, Y. Cao, Y. Wang, H. Yang, “Technological exploration of RRAM crossbar array for matrix-vector multiplication,” Journal of Computer Science and Technology, China, vol. 31, no. 1, pp. 3-19, January 2016.

  15. N. Suda, J. Suh, N. Hakim, Y. Cao, B. Bakkaloglu, “A 65nm Programmable ANalog Device Array (PANDA) for analog circuit emulation,” IEEE Transactions on Circuits and Systems I, vol. 63, no. 2, pp. 181-190, February 2016.

    2015

  16. S. Yu, P.-Y. Chen, Y. Cao, Y. Wang, H. Wu, “Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect,” International Electron Devices Meeting, pp. 451-454, 2015. [invited]
  17.  Y. Ma, M. Kim, A. Mohanty, J. Seo, Y. Cao, S. Vrudhula, “Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits,” International Conference on Computer Design, pp. 443-446, 2015.
  18. M. Mao, Y. Cao, S. Yu, C. Chakrabarti, “Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings,” International Conference on Computer Design, pp. 359-366, 2015.
  19. M. Mao, Y. Cao, S. Yu, C. Chakrabarti, “Programming strategies to improve energy efficiency and reliability of ReRAM memory systems,” IEEE Workshop on Signal Processing Systems, pp. 1-6, 2015.
  20. A. R. Subramaniam, J. Roveda, Y. Cao, “A finite-point method for efficient gate characterization under multiple input switching,” ACM Transactions on Design Automation of Electronic Systems., vol. 21, no. 1, article 10, pp. 10.1-10.25, November 2015.
  21. J. Seo, B. Lin, M. Kim, P.-Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, S. Vrudhula, S. Yu, J. Ye, Y. Cao, “On-chip sparse learning acceleration with CMOS and resistive synaptic devices,” IEEE Transactions on Nanotechnology, Special Issue on Cognitive and Natural Computing with Nanotechnology, vol. 14, no. 6, pp. 969-979, November 2015.
  22. L. Gao, I-T. Wang, P.-Y. Chen, S. Vrudhula, J. Seo, Y. Cao, T.-H. Hou, S. Yu, “Fully parallel Write/Read in resistive synaptic array for accelerating on-chip learning,” Nanotechnology, IOP Science, vol. 26-455204, pp. 1-9, November 2015.
  23. P.-Y. Chen, B. Lin, I.-T. Wang, T.-H. Hou, J. Ye, J. Seo, S. Vrudhula, Y. Cao, S. Yu, “Mitigating effects of non-ideal synaptic device characteristics for on-chip learning,” International Conference on Computer Aided Design, pp. 194-199, 2015.
  24. K. B. Sutaria, A. Mohanty, R. Wang, R. Huang, Y. Cao, “Accelerated aging in analog and digital circuits with feedback,” IEEE Transactions on Device and Materials Reliability, vol. 15, no. 3, pp. 384-393, September 2015.
  25. P.-Y. Chen, Y. Cao, C. Chakrabarti, S. Yu, “Exploiting resistive cross-point array for compact design of physical unclonable function,” IEEE Symposium on Hardware-Oriented Security and Trust, pp. 26-31, 2015.
  26. D. Kadetotad, Z. Xu, A. Mohanty, P.-Y. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, J. Seo, “Parallel architecture with resistive crosspoint array for dictionary learning acceleration,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Special Issue on Solid-State Memristive Devices and Systems, vol. 5, no. 2, pp. 194-204, June 2015.
  27. R. Wang, Y. Cao, “Impact of temporal transistor variations on circuit reliability,” IEEE International Symposium on Circuits and Systems, pp. 2453-2456, 2015. [invited]
  28. S. Yu, Y. Cao, “On-chip sparse learning with resistive cross-point array architecture,” Great Lakes Symposium on VLSI, pp. 195-197, 2015. [invited]
  29. K. B. Sutaria, P. Ren, A. Mohanty, X. Feng, R. Wang, R. Huang, Y. Cao, “Duty cycle shift under static/dynamic aging in 28nm HK-MG technology,” International Reliability Physics Symposium, CA.7.1-CA.7.5, 2015.
  30. K. B. Sutaria, X. Feng, P. Ren, R. Wang, R. Huang, Y. Cao, “Joint impact of PBTI and CHC on bias runaway at 28nm,” Government Microcircuit Applications & Critical Technology Conference, pp. 24.1.1-24.1.4, 2015.
  31. A. Subramaniam, J. Roveda, Y. Cao, “Finite-point method for efficient timing characterization of sequential elements,” Integration, the VLSI Journal, Elsevier Ltd., vol. 49, pp. 104-113, March 2015.
  32. P.-Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, B. Lin, J. Ye, S. Vrudhula, J. Seo, Y. Cao, S. Yu, “Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip,” Design, Automation & Test in Europe, pp. 854-859, 2015.
  33. P. Gu, B. Li, T. Tang, S. Yu, Y. Wang, Y. Cao, “Technological exploration of RRAM crossbar array for matrix-vector multiplication,” Asia and South Pacific Design Automation Conference, pp. 106-111, 2015. 
  34. 2014

  35. C. Yang, Z. Xu, K. Sutaria, C. Chakrabarti, Y. Cao, “Design exploration of heterogeneous memory technologies,” Chapter 19, pp. 407-427, in VLSI: Circuits for Emerging Applications, Edited by T. Wojcicki, CRC Press, 2014.
  36. G. Wirth, Y. Cao, J. B. Velamala, K. B. Sutaria, T. Sato, “Charge trapping in MOSFETs: BTI and RTN modeling for circuits,” pp. 751-782, Bias Temperature Instability for Devices and Circuits, Edited by T. Grasser, Springer, 2014.
  37. K. Sutaria, J. Velamala, V. Ravi, G. Wirth, T. Sato, Y. Cao, “Multilevel reliability simulation for IC design,” pp. 719-749, Bias Temperature Instability for Devices and Circuits, Edited by T. Grasser, Springer, 2014.
  38. Z. Xu, M. Cavaliere, P. An, S. Vrudhula, Y. Cao, “The stochastic loss of spikes in Spiking Neural P systems: Design and implementation of reliable arithmetic circuits,” Fundamenta Informaticae, Special Issue on Computational Aspects of Bio-processes, vol. 134, no. 1-2, pp. 183-200, 2014. 
  39. Z. Xu, C. Yang, M. Mao, K. Sutaria, C. Chakrabarti, Y. Cao, “Compact modeling of STT-MTJ devices,” Solid-State Electronics, Elsevier Ltd., Special Issue on the 2013 European Solid-State Device Research & Circuits Conference, vol. 102, pp. 76-81, December 2014.
  40. D. Kadetotad, Z. Xu, A. Mohanty, P.-Y. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, J. Seo, “Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning,” IEEE Biomedical Circuits and Systems Conference, pp. 536-539, 2014.
  41. M. Mao, C. Yang, Z. Xu, Y. Cao, C. Chakrabarti, “Low cost ECC schemes for improving the reliability of DRAM+PRAM main memory,” IEEE Workshop on Signal Processing Systems, pp. 1-6, 2014. 
  42. Z. Xu, A. Mohanty, P.-Y. Chen, D. Kadetotad, B. Lin, J. Ye, S. Vrudhula, S. Yu, J. Seo, Y. Cao, “Parallel programming of resistive cross-point array for synaptic plasticity,” Procedia Computer Science, Elsevier Ltd., 5th Annual International Conference on Biologically Inspired Cognitive Architectures, vol. 41, pp. 126-133, November 2014.
  43. X. Feng, P. Ren, Z. Ji, R. Wang, K. B. Sutaria, Y. Cao, R. Huang, “Novel voltage step stress (VSS) technique for fast lifetime prediction of hot carrier degradation,” International Conference on Solid-State and Integrated Circuit Technology, pp. 1-3, 2014.
  44. C. Yang, Y. Emre, Z. Xu, H. Chen, Y. Cao, C. Chakrabarti, “A low cost multi-tiered approach to improving the reliability of multi-level cell PRAM,” Journal of Signal Processing Systems, Elsevier Ltd., Special Issue on the 2012 IEEE Workshop on Signal Processing Systems, vol. 76, no. 2, pp. 133-147, August 2014.
  45. Z. Xu, M. Cavaliere, P. An, S. Vrudhula, Y. Cao, “The stochastic loss of spikes in spiking neural P systems: Design and implementation of reliable arithmetic circuits,” The 12th Brainstorming Week on Membrane Computing, pp. 353-373, 2014.
  46. K. B. Sutaria, A. Ramkumar, R. Zhu, Y. Cao, “Where is the Achilles heel under circuit aging,” IEEE Computer Society Annual Symposium on VLSI, pp. 278-279, 2014. [invited]
  47. K. B. Sutaria, J. B. Velamala, C. Kim, T. Sato, Y. Cao, “Aging statistics based on trapping/detrapping: compact modeling and silicon validation,” IEEE Transactions on Device and Materials Reliability, vol. 14, no. 2, pp. 607-615, June 2014.
  48. K. B. Sutaria, P. Ren, X. Feng, A. Ramkumar, R. Zhu, R. Wang, R. Huang, Y. Cao, “Diagnosing bias runaway in analog/mixed signal circuits,” International Reliability Physics Symposium, 2D.3.1-2D.3.4, 2014.
  49. K. B. Sutaria, A. Ramkumar, R. Zhu, Y. Ma, Y. Cao, “BTI-induced aging under random stress waveforms: modeling, simulation and silicon validation,” Design Automation Conference, pp. 1-6, 2014.
  50. M. Bajura, J. Ahlbin, I. S. Esqueda, S. Stansberry, P. Gadfort, M. Fritze, A. Ramkumar, K. Sutaria, Y. Cao, T.-F. Wu, C.-R. Ho, M. Chen, “Assessing long-term CMOS reliability for government IC applications,” Government Microcircuit Applications & Critical Technology Conference, pp. 399-402, 2014.
  51. X. Chen, Y. Wang, Y. Cao, H. Yang, “Statistical analysis of random telegraph noise in digital circuits,” Asia and South Pacific Design Automation Conference, pp. 161-166, 2014. [best paper award nominee]
  52. Y. Cao, J. Velamala, K. Sutaria, M. S.-W. Chen, J. Ahlbin, I. S. Esqueda, M. Bajura, M. Fritze, “Cross-layer modeling and simulation of circuit reliability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 1, pp. 8-23, January 2014. [Keynote]
  53. 2013

  54. J. B. Velamala, K. B. Sutaria, H. Shimuzu, H. Awano, T. Sato, G. Wirth, Y. Cao, “Compact modeling of statistical BTI under trapping/detrapping,” IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3645-3654, November 2013.
  55. Z. Xu, K. B. Sutaria, C. Yang, C. Chakrabarti, Y. Cao, “Compact modeling of STT-MTJ for SPICE simulation,” European Solid-State Device Research & Circuits Conference, pp. 338-341, 2013.
  56. M. Chen, V. Reddy, S. Krishnan, J. Ondrusek, and Y. Cao “ACE: A robust variability and aging sensor for high-k/metal gate SoC,” European Solid-State Device Research & Circuits Conference, pp. 182-185, 2013.
  57. X. Chen, H. Luo, Y. Wang, Y. Cao, Y. Xie, Y. Ma, H. Yang, “Evaluation and mitigation of performance degradation under RTN for digital circuits,” IET Circuits, Devices & Systems., Special Issue on Design Methodologies for Nanoelectronic Digital and Analogue Circuits, vol. 7, no. 5, pp. 273-282, September 2013. [invited]
  58. S. Yang, W. Wang, M. Hagan, W. Zhang, P. Gupta, Y. Cao, “NBTI aware circuit node criticality computation,” ACM Journal of Emerging Technologies in Computing Systems, vol. 9, no. 3, pp. 23:1-19, September 2013.
  59. J. Velamala, K. Sutaria, H. Shimizu, H. Awano, T. Sato, G. Wirth, Y. Cao, “Logarithmic modeling of BTI under dynamic circuit operations: static, dynamic and long-term prediction,” International Reliability Physics Symposium, CM.3.1-CM.3.5, 2013.
  60. J. B. Velamala, K. B. Sutaria, V. Ravi, Y. Cao, “Failure analysis of asymmetric aging under NBTI,” IEEE Transactions on Device and Materials Reliability, vol. 13, no. 2, pp. 340-349, June 2013. [invited] 
  61. J. Suh, N. Suda, C. Xu, N. Hakim, Y. Cao, B. Bakkaloglu, “Programmable analog device array (PANDA): a methodology for transistor-level analog emulation,” IEEE Transactions on Circuits and Systems I, vol. 60, no. 6, pp. 1369-1380, June 2013.
  62. J. Ahlbin, I. S. Esqueda, S. Stansberry, G. Boverman, M. Bajura, M. Fritze, C.-R. Ho, J. Hayong, L. Tian, N. Upadhyay, M. Chen, J. Velamala, K. Sutaria, V. Ravi, Y. Cao, “Techniques for estimating reliability for digital and analog CMOS circuits,” Government Microcircuit Applications & Critical Technology Conference, 38-5.1-38-5.4, 2013. 

    2012

  63. W. Xu, S. Sinha, H. Wu, T. Dastagir, Y. Cao and H. Yu, “On-chip spiral inductors with integrated magnetic materials,” Chapter 17, pp. 439-462,  Advanced Circuits for Emerging Technologies, Edited by Kris Iniewski, John Wiley & Sons, Inc., 2012.
  64. J. Sun, R. Zheng, J. B. Velamala, Y. Cao, R. Lysecky, K. V. Shankar, J. Roveda, “A self-evolving design methodology for power efficient multi-core systems,” ACM Transactions on Design Automation of Electronic Systems, Special Issue on Adaptive Power Management for Energy and Temperature Aware Computing Systems, vol. 18, no. 1, pp. 4:1-4:24, December 2012.
  65. Z. Xu, K. Sutaria, C. Yang, C. Chakrabarti, Y. Cao, “SPICE modeling of STT-RAM for resilient design,” 5th International MOS-AK/GSA Workshop, San Francisco, CA, 2012.
  66. X. Chen, Y. Wang, Y. Cao, Y. Ma, and H. Yang, “Variation-aware supply voltage assignment for simultaneous power and aging optimization,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 11, pp. 2143-2147, November 2012. 
  67. C.-C. Wang, Y. Ye, Y. Cao, “The potential of Fe-FET for robust design under variations: a compact modeling study,” Microelectronics Journal, Elsevier Ltd., vol. 43, no. 11, pp. 898-903, November 2012.
  68. Y. Emre, C. Yang, K. Sutaria, Y. Cao, C. Chakrabarti, “Enhancing the reliability of STT-RAM through circuit and system level techniques,” IEEE Workshop on Signal Processing Systems, pp. 125-130, 2012.
  69. C. Yang, Y. Emre, Y. Cao, C. Chakrabarti, “Multi-tiered approach to improving the reliability of multi-level cell PRAM,” IEEE Workshop on Signal Processing Systems, pp. 114-119, 2012.
  70. K. Sutaria, J. B. Velamala, Y. Cao, “Multi-level reliability simulation for IC design,” International Conference on Solid-State and Integrated Circuit Technology, S07-03, pp. 1-4, 2012. [invited]
  71. C. Yang, Y. Emre, Y. Cao, C. Chakrabarti, “Improving reliability of non-volatile memory technologies through circuit level techniques  and error control coding,” EURASIP Journal on Advances in Signal Processing., vol. 2012, no. 211, pp. 1-24, October 2012.
  72. Z. Xu, C. Yang, K. Sutaria, C. Chakrabarti, Y. Cao, “Hierarchical modeling of phase change memory for reliable design,” International Conference on Computer Design, pp. 115-120, 2012.
  73. J. B. Velamala, K. Sutaria, H. Shimizu, H. Awano, T. Sato, Y. Cao, “Statistical aging under dynamic voltage scaling: a logarithmic model approach,” Custom Integrated Circuits Conference, 6-3, pp. 1-4, 2012. [best student paper nominee]
  74. H. Luo, Y. Wang, Y. Cao, Y. Xie, H. Yang, “Temporal performance degradation under RTN: evaluation and mitigation for nanoscale circuits," IEEE Computer Society Annual Symposium on VLSI, pp. 183-188, 2012. [best paper award]
  75. S. Sinha, G. Yeric, B. Cline, V. Chandra, Y. Cao, “Design benchmarking to 7nm with FinFET predictive technology models,” International Symposium on Low Power Electronics and Design, pp. 15-20, 2012.
  76. S. Sinha, G. Yeric, V. Chandra, B. Cline, Y. Cao, “Exploring sub-20nm FinFET design with predictive technology models,” Design Automation Conference, pp. 283-288, 2012.
  77. J. Velamala, K. Sutaria, H. Shimuzu, T. Sato, Y. Cao, “Physics matters: statistical aging prediction under trapping/detrapping,” Design Automation Conference, pp. 139-144, 2012. [best paper award nominee]
  78. J. B. Velamala, K. B. Sutaria, T. Sato, Y. Cao, “Aging statistics based on trapping/detrapping: silicon evidence, modeling and long-term prediction,” International Reliability Physics Symposium, 2F.2.1-2F.2.5, 2012.
  79. S. Gummalla, A. Subramaniam, Y. Cao, C. Chakrabarti, “An analytical approach to efficient circuit variability analysis in scaled CMOS design,” International Symposium on Quality Electronic Design, pp. 641-647, 2012.
  80. A. Subramaniam, R. Singhal, C.-C. Wang, Y. Cao, “Leakage reduction through optimization of regular layout parameters,” Microelectronics Journal, Elsevier Ltd., vol. 43, no. 1, pp. 25-33, January 2012.
  81. 2011

  82. W. Wang, V. Reddy, S. Krishnan, Y. Cao, “Compact modeling for NBTI and CHC effects,” pp. 40-60, Recent Advancements in Modeling of Semiconductor Processes, Circuits and Chip-Level Interactions, Edited by Rasit Onur Topaloglu and Peng Li, Bentham Science Publishers Ltd., 2011.
  83. Y. Cao, Predictive Technology Model for Robust Nanoelectronic Design, Springer, 2011.
  84. J. Velamala, V. Ravi, Y. Cao, “Failure diagnosis of asymmetric aging under NBTI,” International Conference on Computer Aided Design, pp. 428-433, 2011.
  85. S. Sinha, J. Suh, B. Bakkaloglu, Y. Cao, “Workload-aware neuromorphic design of power controller,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 3, pp. 381-390, September 2011.
  86. H. Luo, Y. Wang, J. Velamala, Y. Cao, Y. Xie, and H. Yang, “The impact of correlation between NBTI and TDDB on the performance of digital circuits,” International Midwest Symposium on Circuits and Systems, pp. 1-4, 2011. [invited]
  87.  S. Sinha, J. Suh, B. Bakkaloglu, Y. Cao, “A workload-aware neuromorphic controller for dynamic power and thermal management,” NASA/ESA Conference on Adaptive Hardware and Systems, pp. 200-207, 2011.
  88. Y. Ye, F. Liu, M. Chen, S. Nassif, and Y. Cao, “Statistical modeling and simulation of threshold variation under random dopant fluctuations and line-edge roughness,” IEEE Transactions on VLSI Systems, vol. 19, no. 6, pp. 987-996, June 2011.
  89. J. Velamala, R. LiVolsi, M. Torres, Y. Cao, “Design sensitivity of single event transients in scaled logic circuits,” Design Automation Conference, pp. 694-699, 2011.
  90. R. Zheng, J. Suh, C. Xu, N. Hakim, B. Bakkaloglu, Y. Cao, “Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurability,” Design Automation Conference, pp. 322-327, 2011. 
  91. E. Mintarno, J. Skaf, R. Zheng, J. Velamala, Y. Cao, S. Boyd, R. W. Dutton, S. Mitra, “Self-tuning for maximized lifetime energy-efficiency in the presence of circuit aging,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 5, pp. 760-773, May 2011.
  92. H. Luo, X. Chen, J. Velamala, Y. Wang, Y. Cao, V. Chandra, Y. Ma, H. Yang, “Circuit-level delay modeling considering both TDDB and NBTI,” International Symposium on Quality Electronic Design, pp. 14-21, 2011.
  93. J. Velamala, C.-C. Wang, R. Zheng, Y. Ye, Y. Cao, “Intrinsic variability and reliability in nano-CMOS,” Electrochemical Society Transactions, vol. 35, no. 4, pp. 353-367, April 2011. [invited]
  94. S. Sinha, J. Suh, B. Bakkaloglu, Y. Cao, “Workload-aware low-power supply voltage controller,” the Neuromorphic Engineer, 10.2417/1201104.003553, pp. 1-3, April 2011.
  95. Y. Wang, X. Chen, W. Wang, Y. Cao, Y. Xie, H. Yang, “Leakage power and circuit aging cooptimization by gate replacement techniques,” IEEE Transactions on VLSI Systems, vol. 19, no. 4, pp. 615-628, April 2011.
  96. W. Xu, S. Sinha, H. Wu, M. Dastagir, D. S. Gardner, Y. Cao, H. Yu, “Sub-100 mm scale on-chip inductors with CoZrTa for GHz applications,” Journal of Applied Physics, vol. 109, no. 7, 07A316, pp. 1-3, April 2011.
  97. M. Chen, V. Reddy, J. Carulli, S. Krishnan, V. Srinivasan, V. Rentala, and Y. Cao, “On-the-fly measurement of data path delay degradation in dynamic operations,” International Reliability Physics Symposium, pp. 36-40, 2011.
  98. R. LiVolsi, K. McCornick, M. Torres, J. Velamala, R. Zheng, Y. Cao, “Correlation of no trouble found errors to negative temperature instability,” IEEE Aerospace Conference, pp. 1-8, 10.1109/AERO.2011.5747585, 2011.
  99. W. Xu, S. Sinha, T. Dastagir, H. Wu, B. Bakkaloglu, D. S. Gardner, Y. Cao, and H. Yu, “Performance enhancement of on-chip inductors with permalloy magnetic rings,” IEEE Electron Device Letters., vol. 32, no. 1, pp. 69-71, January 2011.
  100. 2010

  101. Y. Ye, S. Gummalla, C.-C. Wang, C. Chakrabarti, Y. Cao, “Random variability modeling and its impact on scaled CMOS circuits,” Journal of Computational Electronics, Springer, vol. 9, pp. 108-113, December 2010. [invited]
  102. Y. Cao, C.-C. Wang, Y. Ye, S. Gummalla, C. Chakrabarti, “Intrinsic variability in nano-CMOS design and beyond,” International Electron Devices Meeting, pp. 414, 2010. [invited]
  103. W. Xu, S. Sinha, H. Wu, M. Dastagir, D. S. Gardner, Y. Cao, H. Yu, “Sub-100µm scale on-chip inductors with CoZrTa for GHz applications,” The 55th Magnetism and Magnetic Materials Conference, 2010.
  104. Y. Ye, C.-C. Wang. C.-Y. Chen, Y. Cao, “Simulation of random telegraph noise with 2-stage equivalent circuit,” International Conference on Computer Aided Design, pp. 709-713, 2010.
  105. J. Sun, Y. Cao, J. Wang, “A self-evolving design methodology for power efficient multi-core systems,” International Conference on Computer Aided Design, pp. 264-268, 2010.
  106. C.-Y. Chen, C.-C. Wang, Y. Ye, Y. Liu, J. Sato-Iwanaga, A. Inoue, H. Sorada, Y. Cao, R. W. Dutton, “A physics-based compact model for the 1/f noise in p-type Si/SiGe/Si heterostructure MOSFETs,” The Workshop on Synthesis and System Integration of Mixed Information Technologies, R1-14, 2010.
  107. T. Dastagir, W. Xu, S. Sinha, H. Wu, Y. Cao, and H. Yu, “Tuning the permeability of permalloy films for on-chip inductor applications,” Applied Physics Letters, vol. 97, 162506, pp. 1-3, October 2010.
  108. S. Sinha, A. Balijepalli, Y. Cao, “Compact modeling of carbon nanotube transistor and interconnects,” Chapter 12, pp. 217-236, Carbon Nanotubes, Edited by Jose Mauricio Marulanda, IN-TECH Education and Publishing, 2010.
  109. W. Wang, V. Reddy, V. Balakrishnan, S. Krishnan, Y. Cao, “Statistical prediction of circuit aging under process variations,” Chapter 5, pp. 101-122, Solid State Circuits Technologies, Edited by Jacobus W. Swart, IN-TECH Education and Publishing, 2010.
  110. C.-C. Wang, Y. Ye, Y. Cao, “Compact modeling of Fe-FET and implications on variation-insensitive design,” International Conference on Simulation of Semiconductor Processes and Devices, pp. 247-250, 2010.
  111. S. Sinha, J. Suh, B, Bakkaloglu, Y. Cao, “Workload-aware neuromorphic design of low-power supply voltage controller,” International Symposium on Low Power Electronics and Design, pp. 241-246, 2010.
  112. J. Lee, C.-C. Wang, H. Gashami, L. Bircher, Y. Cao, and N. S. Kim, “Workload-adaptive process tuning strategy for power-efficient multi-core processors,” International Symposium on Low Power Electronics and Design, pp. 225-230, 2010.
  113. S. Chellappa, J. Ni, X. Yao, N. Hindman, J. Velamala, M. Chen, Y. Cao, L. T. Clark, “In-situ characterization and extraction of SRAM variability,” Design Automation Conference, pp. 711-716, 2010.
  114. J. B. Velamala, V. Reddy, R. Zheng, S. Krishnan, Y. Cao, “On the bias dependence of time exponent in NBTI and CHC effects,” International Reliability Physics Symposium, pp. 650-654, 2010.
  115. E. Mintarno, R. Zheng, J. Velamala, Y. Cao, S. Boyd, R. W. Dutton, and S. Mitra, “Optimized self-tuning to maximize lifetime energy-efficiency in the presence of circuit aging,” Design, Automation and Test in Europe, pp. 586-591, 2010.
  116. S. Nassif, N. Mehta, Y. Cao, “A resilience roadmap,” Design, Automation and Test in Europe, pp. 1011-1016, 2010. [invited]
  117. R. Singal, A. Balijepalli, A. Subramaniam, C.-C. Wang, F. Liu, S. Nassif, Y. Cao, “Modeling and analysis of the non-rectangular gate effect for post-lithography circuit simulation,” IEEE Transactions on VLSI Systems, vol. 18, no. 4, pp. 666-670, April 2010.
  118. Y. Cao, F. Liu, “Compact variability modeling in scaled CMOS design,” IEEE Design & Test of Computers, Special Issue on Compact Variability Modeling in Scaled CMOS Design, vol. 27, no. 2, pp. 6-7, March/April 2010.
  119. W. Xu, S. Sinha, F. Pan, T. Dastagir, Y. Cao, H. Yu, “Improved frequency response of on-chip inductors with patterned magnetic dots,” IEEE Electron Device Letters, vol. 31, no. 3, pp. 207-209, March 2010.
  120. W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, Y. Cao, “The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis,” IEEE Transactions on VLSI Systems, vol. 18, no. 2, pp. 173-183, 2010.
  121. Y. Cao, A. Balijepalli, S. Sinha, C.-C. Wang, W. Wang, W. Zhao, “The predictive technology model in the late silicon era and beyond,” Foundations and Trends in Electronic Design Automation, vol. 3, no. 4, pp. 305-401, 2010. [invited]
  122. 2009

  123. Y. Cao, J. Tschanz, P. Bose, “Reliability challenges in nano-CMOS design,” IEEE Design & Test of Computers, Special Issue on Design for Reliability at 32nm and Beyond, vol. 26, no. 6, pp. 6-7, November/December 2009.
  124. C.-C. Wang, W. Zhao, F. Liu, M. Chen, Y. Cao, “Predictive modeling of layout-dependent stress effect in scaled CMOS design,” International Conference on Computer Aided Design, pp. 513-520, 2009.
  125. S. Sinha, W. Xu, J. Velamala, M. Dastagir, B. Bakkaloglu, H. Yu, Y. Cao, “Enabling resonant clock distribution with scaled on-chip magnetic inductors,” International Conference on Computer Design, pp. 103-108, 2009.
  126. M. Chen, W. Zhao, F. Liu, Y. Cao, “Finite-point based transistor model: A new approach to fast circuit simulation,” IEEE Transactions on VLSI Systems, vol. 17, no. 10, pp. 1470-1480, October 2009.
  127. S. Sinha, A. Balijepalli, Y. Cao, “Compact model of carbon nanotube transistor and interconnect,” IEEE Transactions on Electron Devices, vol. 56, no. 10, pp. 2232-2242, October 2009.
  128. R. Zheng, J. Velamala, V. Reddy, V. Balakrishnan, E. Mintarno, S. Mitra, S. Krishnan, Y. Cao, “Circuit aging prediction for low-power operation,” Custom Integrated Circuits Conference, pp. 427-430, 2009.
  129. X. Li, W. Zhao, Y. Cao, Z. Zhu, J. Song, D. Bang, C.-C. Wang, S. H. Kang, J. Wang, M. Nowak, N. Yu, “Pathfinding for 22nm CMOS designs using predictive technology models,” Custom Integrated Circuits Conference, pp. 227-230, 2009.
  130. C.-C. Wang, W. Zhao, M. Chen, Y. Cao, “Compact modeling of stress effects in scaled CMOS,” International Conference on Simulation of Semiconductor Processes and Devices, pp. 1-4, 2009.
  131. A. Balijepalli, J. Ervin, W. Lepkowski, Y. Cao, and T. Thornton, “Compact modeling of a PD SOI MESFET for wide temperature designs,” Microelectronics Journal, Elsevier Ltd., vol. 40, no. 9, pp. 1264-1273, September 2009.
  132. W. Zhao, X. Li, S. Gu, S. H. Kang, M. Nowak, Y. Cao, “Field-based capacitance modeling for sub-65nm on-chip interconnect,” IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 1862-1872, September 2009.
  133. X. Chen, Y. Wang, Y. Cao, Y. Ma, and H. Yang, “Variation-aware supply voltage assignment for minimizing circuit aging and leakage,” International Symposium on Low Power Electronics and Design, pp. 39-44, 2009. [best paper award nominee]
  134. Y. Ye, F. Liu, M. Chen, Y. Cao, “Variability analysis under layout pattern-dependent rapid-thermal annealing process,” Design Automation Conference, pp. 551-556, 2009.
  135. T.-B. Chan, V. Balakrishnan, Y. Cao, P. Gupta, “Extended burn-in for reduced Vth variation,” IEEE International Workshop on Design for Manufacturability and Yield (DFM&Y), pp. 25-28, 2009.
  136. Y. Wang, X. Chen, W. Wang, Y. Cao, Y. Xie, and H. Yang, “Gate replacement techniques for simultaneous leakage and aging optimization,” Design, Automation and Test in Europe, pp. 328-333, 2009.
  137. R. Krishnan, M. Debole, W. Wang, V. Balakrishnan, H. Luo, Y. Wang, Y. Cao, Y. Xie, V. Narayanan, “New-Age: A NBTI-estimation framework for microarchitectural components,” International Journal of Parallel Programming., vol. 37, pp. 417-431, May 2009.
  138. Y. Wang, X. Chen, W. Wang, V. Balakrishnan, Y. Cao, Y. Xie, H. Yang, “On the efficacy of input vector control to mitigate circuit aging and leakage,” International Symposium on Quality Electronic Design, pp. 19-26, 2009.
  139. Y. Cao, “What is Predictive Technology Model (PTM)?” ACM/SIGDA E-Newsletter, vol. 39, no. 3, March 2009. [invited]
  140. Y. Ye, F. Liu, Y. Cao, “Modeling of threshold voltage shift under pattern-dependent RTA process,” SPIE Design for Manufacturability through Design-Process Integration III, vol. 7275, 72751T-1-9, 2009.
  141. C.-C. Wang, W. Zhao, F. Liu, M. Chen, Y. Cao, “Predictive modeling of layout-dependent stress effect in scaled CMOS design,” International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 2009.
  142. J. Ni, M. Chen, X. Lin, Y. Cao, “Adaptive transistor model for fast circuit simulation,” International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 2009.
  143. W. Zhao, F. Liu, K. Agarwal, D. Acharyya, S. R. Nassif, K. Nowka, Y. Cao, “Rigorous extraction of process variations for 65nm CMOS design,” IEEE Transactions on Semiconductor Manufacturing, vol. 22, no. 1, pp. 196-203, February 2009.
  144. M. Debole, R. Krishnan, W. Wang, V. Balakrishnan, H. Luo, Y. Wang, Y. Cao, Y. Xie, V. Narayanan, “New-Age: A framework for NBTI estimation,” Asia and South Pacific Design Automation Conference, pp. 455-460, 2009.
  145. 2008

  146. J. M. Wang, Y. Cao, M. Chen, J. Sun, A. Mitev, and K. Potluri, “Capturing device mismatch in analog and mixed-signal designs,” IEEE Circuits and Systems Magazine., vol. 8, no. 4, pp. 37-44, 2008. [invited]
  147. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, S. Vrudhula, “A scalable model for predicting the effect of NBTI for reliable design,” IET Circuits, Devices & Systems., vol. 2, no. 4, pp. 361-371, 2008.
  148. T. Austin, V. Bertacco, S. Mahlke, Y. Cao, “Reliable systems on unreliable fabrics,” IEEE Design & Test of Computers, vol. 25, no. 4, pp. 322-332, February 2008. [invited]
  149. W. Wang, V. Balakrishnan, B. Yang, Y. Cao, “Statistical prediction of NBTI-induced circuit aging,” International Conference on Solid-State and Integrated-Circuit Technology, pp. 416-419, 2008. [invited]
  150. M. Agarwal, V. Balakrishnan, A. Bhuyan, K. Kim, B. C. Paul, Y. Cao, S. Mitra, “Optimized circuit failure prediction for aging: practicality and promise,” International Test Conference, no. 26.1, 2008.
  151. W. Wang, V. Reddy, B. Yang, V. Balakrishnan, S. Krishnan, Y. Cao, “Statistical prediction of circuit aging under process variations,” Custom Integrated Circuits Conference, pp. 13-16, 2008.
  152. C.-C. Wang, W. Zhao, Y. Cao, “Predictive modeling of layout-dependent carrier mobility in stressed CMOS technology,” SRC TECHNON, 2008.
  153. V. Balakrishnan, W. Wang, Y. Cao, “Statistical prediction of circuit aging under process and design uncertainties,” SRC TECHNON, 2008.
  154. Y. Ye, F. Liu, S. Nassif, Y. Cao, “Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness,” Design Automation Conference, pp. 900-905, 2008.
  155. S. Sinha, A. Balijepalli, Y. Cao, “A simplified model of carbon nanotube transistor with applications to analog and digital design,” International Symposium on Quality Electronic Design, pp. 502-507, 2008.
  156. W. Wang, S. Yang, and Y. Cao, “Node criticality computation for circuit timing analysis and optimization under NBTI effect,” International Symposium on Quality Electronic Design, pp. 763-768, 2008.
  157. X. Li, Y. Cao, “Projection-based piecewise-linear response surface modeling for strongly nonlinear VLSI performance variations,” International Symposium on Quality Electronic Design, pp. 108-113, 2008.
  158. D. Ganesan, A. Mitev, J. Wang, Y. Cao, “Finite-point gate model for fast timing and power analysis,” International Symposium on Quality Electronic Design, pp. 657-662, 2008.
  159. L. Cheng, Y. Lin, L. He, and Y. Cao, “Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability,” International Symposium on Field-Programmable Gate Arrays, pp. 159-168, 2008.
  160. M. Agarwal, V. Balakrishnan, A. Bhuyan, K. Kim, M. Mizuno, B. C. Paul, Y. Cao, S. Mitra, "Optimized circuit fialure prediction for aging: practicality and promise," International Workshop on Timing Issues in teh Spcification and Synthesis of Digital System (TAU), 2008.
  161. B. H. Calhoun, Y. Cao, X. Li, K. Mai, L. T. Pileggi, R. A. Rutenbar, and K. L. Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS,” Proceedings of the IEEE, vol. 96, no. 2, pp. 343-365, February 2008. [invited]
  162. A. Subramaniam, R. Singhal, C.-C. Wang, Y. Cao, “Design rule optimization of regular layout for leakage reduction in nanoscale design,” Asia and South Pacific Design Automation Conference, pp. 474-479, 2008.
  163. 2007

  164. W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda, S. Krishnan, Y. Cao, “Compact modeling and simulation of circuit reliability for 65nm CMOS technology,” IEEE Transactions on Device and Materials Reliability, vol. 7, no. 4, pp. 509-517, December 2007. [invited]
  165. Y. Cao and L. T. Clark, “Mapping statistical process variations toward circuit performance variability: an analytical modeling approach,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 10, pp. 1866-1873, October 2007.
  166. W. Zhao and Y. Cao, “Predictive technology model for nano-CMOS design exploration,” ACM Journal on Emerging Technologies in Computing Systems, vol. 3, no. 1, pp. 1-17, April 2007.
  167. W. Zhao, X. Li, M. Nowak, and Y. Cao, "Predictive technology modeling for 32nm low power design," to be published at International Semiconductor Device Research Symposium, 2007.
  168. W. Wang, Z. Wei, S. Yang, Y. Cao, “An efficient method to identify critical gates under circuit aging,” International Conference on Computer Aided Design, pp. 735-740, 2007.
  169. D. Ganesan, D. Shanmugasundaram, A. Mitev, Y. Cao, J. Wang, “A robust finite-point based gate model considering process variations,” International Conference on Computer Aided Design, pp. 692-697, 2007.
  170. Y. Cao, C. C. McAndrew, “MOSFET modeling for 45nm and beyond,” embedded tutorial, International Conference on Computer Aided Design, pp. 638-643, 2007. [invited]
  171. W. Wang, V. Reddy, A. T. Krishnan, S. Krishnan, Y. Cao, “An integrated modeling paradigm of circuit reliability for 65nm CMOS technology,” Custom Integrated Circuits Conference, pp. 511-514, 2007.
  172. W. Zhao, F. Liu, K. Agarwal, D. Acharyya, S. Nassif, K. Nowka, Y. Cao, “Rigorous extraction of process variations for 65nm CMOS design,” European Solid-State Circuits Conference, pp. 89-92, 2007.
  173. W. Wang, V. Reddy, A. T. Krishnan, S. Krishnan, Y. Cao, “An integrated modeling paradigm of circuit reliability for 65nm CMOS technology,” SRC TECHNON, 2007.
  174. A. Balijepalli, S. Sinha, Y. Cao, “Compact modeling of carbon nanotube transistor for early stage process-design exploration,” International Symposium on Low Power Electronics and Design, pp. 2-7, 2007. [best paper award]
  175. W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, F. Liu, S. Vrudhula, Y. Cao, “The impact of NBTI on the performance of combinational and sequential circuits,” Design Automation Conference, pp. 364-369, 2007. [PDF]
  176. R. Singhal, A. Balijepalli, A. Subramaniam, F. Liu, S. Nassif, Y. Cao, “Modeling and analysis of non-rectangular gate for post-lithography circuit simulation,” Design Automation Conference, pp. 823-828, 2007.
  177. M. Chen, W. Zhao, F. Liu, Y. Cao, “Fast statistical circuit analysis with finite-point based transistor model,” Design, Automation and Test in Europe, pp. 1391-1396, 2007.
  178. A. Balijepalli, J. Ervin, Y. Cao, and T. Thornton, “Compact modeling of a PD SOI MESFET for wide-temperature designs,” International Symposium on Quality Electronic Design, pp. 133-138, 2007.
  179. R. Vattikonda, Y. Luo, A. Gyure, X. Qi, S. Lo, M. Shahram, Y. Cao, K. Singhal, and D. Toffolon, “A new simulation method for NBTI analysis in SPICE environment,” International Symposium on Quality Electronic Design, pp. 41-46, 2007.
  180. T. Sairam, W. Zhao, Y. Cao, “Optimizing FinFET technology for high-speed and low-power design,” Great Lakes Symposium on VLSI, pp. 73-77, 2007. [best paper award nominee]
  181. 2006

  182. H. Qin, R. Vattikonda, T. Trinh, Y. Cao, J. Rabaey, “SRAM cell optimization for ultra-low power standby,” ASP Journal of Low Power Electronics, vol. 2, no. 3, pp. 401-411, December 2006.
  183. W. Zhao, Y. Cao, “New generation of predictive technology model for sub-45nm early design exploration,” IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2816-2823, November 2006.
  184. J. He, M. Fang, B. Li, G. Zhang, Y. Cao, “A new analytic approximation to general diode equation,” Elsevier Solid-State Electronics, vol. 50, no. 9, pp. 1371-1374, September 2006.
  185. S. Bhardwaj, Y. Cao, S. Vrudhula, “Statistical leakage minimization of digital circuits using gate sizing, gate length biasing, and threshold voltage selection,” ASP Journal of Low Power Electronics, vol. 2, no. 2, pp. 240-250, August 2006.
  186. B. T. Cline, K. Chopra, D. Blaauw, and Y. Cao “Analysis and modeling of CD variation for statistical static timing,” International Conference on Computer Aided Design, pp. 60-66, 2006.
  187. Y. Cao, W. Zhao, “Predictive technology model for nano-CMOS design exploration,” International Conference on Nano-Networks, 2006. [invited]
  188. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, S. Vrudhula, “Predictive modeling of the NBTI effect for reliable design,” Custom Integrated Circuits Conference, pp. 189-192, 2006.
  189. R. Vattikonda, W. Wang, Y. Cao, “Modeling and minimization of PMOS NBTI effect for robust nanometer design,” Design Automation Conference, pp. 1047-1052, 2006.
  190. S. Bhardwaj, S. Vrudhula, Praveen Ghanta, Y. Cao, “Modeling of intra-die process variations for accurate analysis and optimization of nanoscale circuits,” Design Automation Conference, pp. 791-796, 2006.
  191. A. Balijepalli, J. Ervin, P. Joshi, J. Yang, Y. Cao, and T. J. Thornton, “High-voltage CMOS compatible SOI MESFET characterization and SPICE model extraction,” IEEE International Microwave Symposium, pp. 1335-1338, 2006.
  192. S. Bhardwaj, S. Vrudhula, and Y. Cao, “LOTUS: leakage optimization under timing uncertainty for standard-cell designs,” International Symposium on Quality electronic Design, pp. 717-722, 2006.
  193. W. Zhao and Y. Cao, “New generation of predictive technology model for sub-45nm design exploration,” International Symposium on Quality Electronic Design, pp. 585-590, 2006. [best paper award nominee]
  194. M. Chen and Y. Cao, “Analysis of pulse signaling for low-power on-chip global bus design,” International Symposium on Quality electronic Design, pp. 401-406, 2006.
  195. S. Bhardwaj, Y. Cao, and S. Vrudhula, “Statistical leakage minimization using gate sizing, gate length biasing and threshold voltage selection,” Asia and South Pacific Design Automation Conference, pp. 953-958, 2006. [best paper award nominee]
  196. 2005

  197. J. Chen, L. T. Clark, and Y. Cao, “Maximum Fan-In/Out: Ultra-low voltage circuit design in the presence of variations,” IEEE Circuits and Devices Magazine, vol. 21, no. 6, pp. 12-20, November 2005.
  198. Y. Cao, X.-D. Yang, X. Huang, and D. Sylvester, "Switch-factor based loop RLC modeling for efficient timing analysis," IEEE Transactions on VLSI Systems, vol. 13, no. 9, pp. 1072-1078, September 2005.
  199. H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. M. Rabaey, "Standby supply voltage minimization for deep sub-micron SRAM," Elsevier Microelectronics Journal, vol. 36, no. 9, pp. 789-800, September 2005.
  200. Y. Cao, X. Huang, D. Sylvester, T.-J. King, and C. Hu, "Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design," IEEE Transactions on VLSI Systems, vol. 13, no. 1, pp. 158-162, January 2005.
  201. J. Chen, L. T. Clark, Y. Cao, “Robust subthreshold design of high fan-in/out circuits,” International Conference on Computer Design, pp. 405-410, 2005.
  202. Y. Cao and L. T. Clark, “Mapping statistical process variations toward circuit performance variability: an analytical modeling approach,” Design Automation Conference, pp. 658-663, 2005.
  203. P. Friedberg, Y. Cao, J. Cain, R. Wang, J. Rabaey, and C. Spanos, “Modeling within-die spatial correlation effects for process-design co-optimization,” Microlithography Program, SPIE, 2005.
  204. P. Friedberg, Y. Cao, J. Cain, R. Wang, J. Rabaey, and C. Spanos, “Modeling within-die spatial correlation effects for process-design co-optimization,” International Symposium on Quality Electronic Design, pp. 516-521, 2005.