
Publications
2016

C. Yang, M. Mao, Y. Cao, C. Chakrabarti, “Costeffective
design solutions for enhancing PRAM reliability and performance,” to be
published in IEEE Transactions on MultiScale Computing Systems.

P.Y. Chen, J. Seo, Y. Cao, S. Yu, “Compact oscillation neuron
exploiting metalinsulatortransition for neuromorphic computing,” International
Conference on Computer Aided Design, a15.16, 2016.

Y. Ma, N. Suda, J. Seo, Y. Cao, S.
Vrudhula, “Scalable and modularized RTL compilation of
convolutional neural networks onto FPGA,” International
Conference on FieldProgrammable Logic and Applications,
S5b.18, 2016.

M. Mao, Y. Cao, S. Yu, C. Chakrabarti, “Optimizing
latency, energy, and reliability of 1T1R ReRAM through
crosslayer techniques,” to be published in IEEE
Journal on Emerging and Selected Topics in Circuits and
Systems, Special Issue on Emerging Memory Technology,
Architecture and Applications, vol. 6, no. 3, pp. 352363,
September, 2016.

M. Tu, V. Berisha, Y. Cao, J. Seo,
“Reducing the model order of deep neural networks using
information theory,” IEEE Computer Society Annual
Symposium on VLSI, pp. 9398, arXiv 1605.04859, 2016. [invited]

S. Yin, Y. Ma, Y. Liu, C. Bae, S. Kim, S.
Vrudhula, J. He, Y. Cao, J. Seo, “Lowpower ECG biometric
authentication for wearable systems featuring sparse memory
compression,” ICML 2016 Workshop on Ondevice Intelligence,
pp. 15, 2016.

A. Shrivastava, P. K. Deo, Z. Xu, P.Y.
Chen, S. Yu, Y. Cao, C. Chakrabarti, “Design of a reliable
RRAMbased PUF for compact hardware security primitives,”
International Symposium on Circuits and Systems, pp.
23262329, 2016.

A. Mohanty, N. Suda, M. Kim, S.
Vrudhula, J. Seo, Y. Cao, “Highperformance face detection
with CPUFPGA acceleration,” International Symposium
on Circuits and Systems, pp. 117120, 2016. [invited]

Z. Xu, P.Y. Chen, J. Seo, S. Yu, Y. Cao,
“Hardwareefficient learning with feedforward inhibition,”
International Nanoelectronics Conference, W51, pp. 12, 2016. [invited]

M. Tu, V. Berisha, M. Woolf, J. Seo, Y. Cao,
“Ranking the parameters of deep neural networks using the
Fisher information,” International Conference on Acoustics,
Speech and Signal Processing, pp. 26472651, 2016.

Y. Cao, S. Yu, Y. Wang, P.Y. Chen, L. Xia, H.
Yang, “Neuromorphic computing with resistive synaptic arrays:
devices, circuits and systems,” International
Symposium on Quality Electronic Design, 2016. [invited]

L. Xia, P.Y. Chen, Y. Cao, S. Yu, Y. Wang, H.
Yang, “MNSIM: Simulation platform for memristorbased
neuromorphic computing system,” Design, Automation & Test in
Europe, pp. 469474, 2016.

N. Suda, V. Chandra, G. Dasika, A. Mohanty, Y.
Ma, S. Vrudhula, J. Seo, Y. Cao, “Throughputoptimal
OpenCLbased FPGA accelerator for largescale convolutional
neural networks,” International Symposium on
FieldProgrammable Gate Arrays, pp. 1625, 2016.

L. Xia, P. Gu, B. Li, T. Tang, X. Yin, W.
Huang, S. Yu, Y. Cao, Y. Wang, H. Yang, “Technological
exploration of RRAM crossbar array for matrixvector
multiplication,” Journal of Computer Science and
Technology, China, vol. 31, no. 1, pp. 319, January 2016.
N. Suda, J. Suh, N. Hakim, Y. Cao, B.
Bakkaloglu, “A 65nm Programmable ANalog Device Array (PANDA)
for analog circuit emulation,” IEEE Transactions on Circuits
and Systems I, vol. 63, no. 2, pp. 181190, February 2016.
2015
 S. Yu, P.Y. Chen, Y. Cao, Y. Wang, H. Wu, “Scalingup
resistive synaptic arrays for neuroinspired architecture:
Challenges and prospect,” International Electron Devices
Meeting, pp. 451454, 2015. [invited]
 Y. Ma, M. Kim, A. Mohanty, J. Seo, Y. Cao, S.
Vrudhula, “Energyefficient reconstruction of
compressively sensed bioelectrical signals with stochastic
computing circuits,” International Conference on
Computer Design, pp. 443446, 2015.
 M. Mao, Y. Cao, S. Yu, C.
Chakrabarti, “Optimizing latency, energy, and
reliability of 1T1R ReRAM through appropriate voltage settings,”
International Conference on Computer Design, pp. 359366, 2015.

M. Mao, Y. Cao, S. Yu, C. Chakrabarti, “Programming
strategies to improve energy efficiency and reliability of ReRAM
memory systems,” IEEE Workshop on Signal Processing
Systems, pp. 16, 2015.
 A. R. Subramaniam, J. Roveda, Y. Cao,
“A finitepoint method for efficient gate
characterization under multiple input switching,” ACM
Transactions on Design Automation of Electronic Systems., vol.
21, no. 1, article 10, pp. 10.110.25, November 2015.
 J. Seo, B. Lin, M. Kim, P.Y. Chen, D. Kadetotad, Z. Xu, A.
Mohanty, S. Vrudhula, S. Yu, J. Ye, Y. Cao, “Onchip
sparse learning acceleration with CMOS and resistive synaptic
devices,” IEEE Transactions on Nanotechnology, Special
Issue on Cognitive and Natural Computing with Nanotechnology,
vol. 14, no. 6, pp. 969979, November 2015.
 L. Gao, IT. Wang, P.Y. Chen, S. Vrudhula, J. Seo, Y. Cao,
T.H. Hou, S. Yu, “Fully parallel Write/Read in
resistive synaptic array for accelerating onchip learning,”
Nanotechnology, IOP Science, vol. 26455204, pp. 19, November
2015.
 P.Y. Chen, B. Lin, I.T. Wang, T.H. Hou, J. Ye, J. Seo, S.
Vrudhula, Y. Cao, S. Yu, “Mitigating effects of
nonideal synaptic device characteristics for onchip learning,”
International Conference on Computer Aided Design, pp. 194199,
2015.
 K. B. Sutaria, A. Mohanty, R. Wang, R. Huang, Y. Cao, “Accelerated
aging in analog and digital circuits with feedback,” IEEE Transactions on
Device and Materials Reliability, vol. 15, no. 3, pp. 384393,
September 2015.
 P.Y. Chen, Y. Cao, C. Chakrabarti, S. Yu, “Exploiting
resistive crosspoint array for compact design of physical
unclonable function,” IEEE Symposium on
HardwareOriented Security and Trust, pp. 2631, 2015.
 D.
Kadetotad, Z. Xu, A. Mohanty, P.Y. Chen, B. Lin, J. Ye, S.
Vrudhula, S. Yu, Y. Cao, J. Seo, “Parallel architecture
with resistive crosspoint array for dictionary learning
acceleration,” IEEE Journal on Emerging and
Selected Topics in Circuits and Systems, Special Issue on
SolidState Memristive Devices and Systems, vol. 5, no. 2, pp.
194204, June 2015.
 R. Wang, Y. Cao, “Impact of temporal transistor
variations on circuit reliability,” IEEE International
Symposium on Circuits and Systems, pp. 24532456, 2015. [invited]
 S. Yu, Y. Cao, “Onchip sparse learning with
resistive crosspoint array architecture,” Great Lakes
Symposium on VLSI, pp. 195197, 2015. [invited]
 K. B. Sutaria, P. Ren, A. Mohanty, X. Feng, R. Wang, R.
Huang, Y. Cao, “Duty cycle shift under static/dynamic
aging in 28nm HKMG technology,” International
Reliability Physics Symposium, CA.7.1CA.7.5, 2015.
 K. B.
Sutaria, X. Feng, P. Ren, R. Wang, R. Huang, Y. Cao, “Joint
impact of PBTI and CHC on bias runaway at 28nm,”
Government Microcircuit Applications & Critical Technology
Conference, pp. 24.1.124.1.4, 2015.
 A. Subramaniam, J.
Roveda, Y. Cao, “Finitepoint method for efficient
timing characterization of sequential elements,”
Integration, the VLSI Journal, Elsevier Ltd., vol. 49, pp.
104113, March 2015.
 P.Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, B. Lin, J. Ye,
S. Vrudhula, J. Seo, Y. Cao, S. Yu, “Technologydesign
cooptimization of resistive crosspoint array for accelerating
learning algorithms on chip,” Design, Automation & Test
in Europe, pp. 854859, 2015.
 P. Gu, B. Li, T. Tang, S. Yu,
Y. Wang, Y. Cao, “Technological exploration of RRAM
crossbar array for matrixvector multiplication,” Asia
and South Pacific Design Automation Conference, pp. 106111,
2015.
2014
 C. Yang, Z. Xu, K. Sutaria, C. Chakrabarti, Y. Cao, “Design
exploration of heterogeneous memory technologies,”
Chapter 19, pp. 407427, in
VLSI: Circuits for Emerging Applications, Edited by T.
Wojcicki, CRC Press, 2014.
 G. Wirth, Y. Cao, J. B. Velamala, K. B. Sutaria, T. Sato, “Charge
trapping in MOSFETs: BTI and RTN modeling for circuits,”
pp. 751782,
Bias Temperature Instability for Devices and
Circuits, Edited by T. Grasser, Springer, 2014.
 K. Sutaria, J. Velamala, V. Ravi, G. Wirth, T. Sato, Y. Cao,
“Multilevel reliability simulation for IC design,”
pp. 719749,
Bias Temperature Instability for Devices and
Circuits, Edited by T. Grasser, Springer, 2014.
 Z. Xu, M. Cavaliere, P. An, S. Vrudhula, Y. Cao, “The
stochastic loss of spikes in Spiking Neural P systems: Design
and implementation of reliable arithmetic circuits,”
Fundamenta Informaticae, Special Issue on Computational Aspects
of Bioprocesses, vol. 134, no. 12, pp. 183200, 2014.
 Z. Xu, C. Yang, M. Mao, K. Sutaria, C. Chakrabarti, Y. Cao,
“Compact modeling of STTMTJ devices,”
SolidState Electronics, Elsevier Ltd., Special Issue on
the 2013 European SolidState Device Research & Circuits
Conference, vol. 102, pp. 7681, December 2014.
 D. Kadetotad, Z. Xu, A. Mohanty, P.Y. Chen, B. Lin, J. Ye,
S. Vrudhula, S. Yu, Y. Cao, J. Seo, “Neurophysicsinspired
parallel architecture with resistive crosspoint array for
dictionary learning,” IEEE Biomedical Circuits and
Systems Conference, pp. 536539, 2014.
 M. Mao, C. Yang, Z. Xu, Y. Cao, C. Chakrabarti, “Low
cost ECC schemes for improving the reliability of DRAM+PRAM main
memory,” IEEE Workshop on Signal Processing Systems,
pp. 16, 2014.
 Z. Xu, A. Mohanty, P.Y. Chen, D. Kadetotad, B. Lin, J. Ye,
S. Vrudhula, S. Yu, J. Seo, Y. Cao, “Parallel
programming of resistive crosspoint array for synaptic
plasticity,” Procedia Computer Science, Elsevier Ltd.,
5th Annual International Conference on Biologically Inspired
Cognitive Architectures, vol. 41, pp. 126133, November 2014.
 X. Feng, P. Ren, Z. Ji, R. Wang, K. B. Sutaria, Y. Cao, R.
Huang, “Novel voltage step stress (VSS) technique for
fast lifetime prediction of hot carrier degradation,”
International Conference on SolidState and Integrated Circuit
Technology, pp. 13, 2014.
 C. Yang, Y. Emre, Z. Xu, H. Chen, Y. Cao, C. Chakrabarti, “A
low cost multitiered approach to improving the reliability of
multilevel cell PRAM,” Journal of Signal Processing
Systems, Elsevier Ltd., Special Issue on the 2012 IEEE Workshop
on Signal Processing Systems, vol. 76, no. 2, pp. 133147,
August 2014.
 Z. Xu, M. Cavaliere, P. An, S. Vrudhula, Y. Cao, “The
stochastic loss of spikes in spiking neural P systems: Design
and implementation of reliable arithmetic circuits,”
The 12th Brainstorming Week on Membrane Computing, pp. 353373,
2014.
 K. B. Sutaria, A. Ramkumar, R. Zhu, Y. Cao, “Where
is the Achilles heel under circuit aging,” IEEE
Computer Society Annual Symposium on VLSI, pp. 278279, 2014. [invited]
 K. B. Sutaria, J. B. Velamala, C. Kim, T. Sato, Y. Cao, “Aging
statistics based on trapping/detrapping: compact modeling and
silicon validation,” IEEE Transactions on Device and
Materials Reliability, vol. 14, no. 2, pp. 607615, June 2014.
 K. B. Sutaria, P. Ren, X. Feng, A. Ramkumar, R. Zhu, R.
Wang, R. Huang, Y. Cao, “Diagnosing bias runaway in
analog/mixed signal circuits,” International
Reliability Physics Symposium, 2D.3.12D.3.4, 2014.
 K. B. Sutaria, A. Ramkumar, R. Zhu, Y. Ma, Y. Cao, “BTIinduced
aging under random stress waveforms: modeling, simulation and
silicon validation,” Design Automation Conference, pp.
16, 2014.
 M. Bajura, J. Ahlbin, I. S. Esqueda, S. Stansberry, P.
Gadfort, M. Fritze, A. Ramkumar, K. Sutaria, Y. Cao, T.F. Wu,
C.R. Ho, M. Chen, “Assessing longterm CMOS reliability
for government IC applications,” Government
Microcircuit Applications & Critical Technology Conference, pp.
399402, 2014.
 X. Chen, Y. Wang, Y. Cao, H. Yang, “Statistical
analysis of random telegraph noise in digital circuits,”
Asia and South Pacific Design Automation Conference, pp. 161166, 2014.
[best paper award nominee]
 Y. Cao, J. Velamala, K. Sutaria, M. S.W. Chen, J. Ahlbin,
I. S. Esqueda, M. Bajura, M. Fritze, “Crosslayer
modeling and simulation of circuit reliability,” IEEE
Transactions on ComputerAided Design of Integrated Circuits and
Systems, vol. 33, no. 1, pp. 823, January 2014. [Keynote]
2013
 J. B. Velamala, K. B. Sutaria, H. Shimuzu, H. Awano, T. Sato,
G. Wirth, Y. Cao, “Compact modeling of statistical BTI
under trapping/detrapping,” IEEE Transactions on Electron
Devices, vol. 60, no. 11, pp. 36453654, November 2013.
 Z. Xu, K. B. Sutaria, C. Yang, C. Chakrabarti, Y. Cao,
“Compact modeling of STTMTJ for SPICE simulation,”
European SolidState Device Research & Circuits Conference, pp.
338341, 2013.
 M. Chen, V. Reddy, S. Krishnan, J. Ondrusek, and Y. Cao “ACE:
A robust variability and aging sensor for highk/metal gate SoC,”
European SolidState Device Research & Circuits Conference, pp.
182185, 2013.
 X. Chen, H. Luo, Y. Wang, Y. Cao, Y. Xie, Y. Ma, H.
Yang, “Evaluation and mitigation of performance
degradation under RTN for digital circuits,” IET
Circuits, Devices & Systems., Special Issue on Design
Methodologies for Nanoelectronic Digital and Analogue Circuits,
vol. 7, no. 5, pp. 273282, September 2013. [invited]
 S. Yang, W. Wang, M. Hagan, W. Zhang, P. Gupta, Y. Cao, “NBTI
aware circuit node criticality computation,” ACM
Journal of Emerging Technologies in Computing Systems, vol. 9,
no. 3, pp. 23:119, September 2013.
 J. Velamala, K. Sutaria, H. Shimizu, H. Awano, T. Sato, G.
Wirth, Y. Cao, “Logarithmic modeling of BTI under
dynamic circuit operations: static, dynamic and longterm
prediction,” International Reliability Physics
Symposium, CM.3.1CM.3.5, 2013.
 J. B. Velamala, K. B. Sutaria, V. Ravi, Y. Cao, “Failure
analysis of asymmetric aging under NBTI,” IEEE
Transactions on Device and Materials Reliability, vol. 13, no.
2, pp. 340349, June 2013. [invited]
 J. Suh, N. Suda, C. Xu, N. Hakim, Y. Cao, B. Bakkaloglu, “Programmable
analog device array (PANDA): a methodology for transistorlevel
analog emulation,” IEEE Transactions on Circuits and
Systems I, vol. 60, no. 6, pp. 13691380, June 2013.
 J. Ahlbin, I. S. Esqueda, S. Stansberry, G. Boverman, M.
Bajura, M. Fritze, C.R. Ho, J. Hayong, L. Tian, N. Upadhyay, M.
Chen, J. Velamala, K. Sutaria, V. Ravi, Y. Cao, “Techniques
for estimating reliability for digital and analog CMOS circuits,”
Government Microcircuit Applications & Critical Technology
Conference, 385.1385.4, 2013.
2012
 W. Xu, S. Sinha, H. Wu, T. Dastagir, Y. Cao and H. Yu, “Onchip
spiral inductors with integrated magnetic materials,”
Chapter 17, pp. 439462, Advanced Circuits for Emerging
Technologies, Edited by Kris Iniewski, John Wiley & Sons, Inc.,
2012.
 J. Sun, R. Zheng, J. B. Velamala, Y. Cao, R. Lysecky, K. V.
Shankar, J. Roveda, “A selfevolving design methodology
for power efficient multicore systems,” ACM
Transactions on Design Automation of Electronic Systems, Special
Issue on Adaptive Power Management for Energy and Temperature
Aware Computing Systems, vol. 18, no. 1, pp. 4:14:24, December
2012.
 Z. Xu, K. Sutaria, C. Yang, C. Chakrabarti, Y. Cao, “SPICE
modeling of STTRAM for resilient design,” 5th International MOSAK/GSA Workshop,
San Francisco, CA, 2012.
 X. Chen, Y. Wang, Y. Cao, Y. Ma, and H. Yang, “Variationaware
supply voltage assignment for simultaneous power and aging
optimization,” IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, vol. 20, no. 11, pp. 21432147,
November 2012.
 C.C. Wang, Y. Ye, Y. Cao, “The potential of FeFET
for robust design under variations: a compact modeling study,”
Microelectronics Journal, Elsevier Ltd., vol. 43, no. 11, pp.
898903, November 2012.
 Y. Emre, C. Yang, K. Sutaria, Y. Cao,
C. Chakrabarti, “Enhancing the reliability of STTRAM
through circuit and system level techniques,” IEEE Workshop on Signal Processing Systems,
pp. 125130, 2012.
 C. Yang, Y. Emre, Y. Cao, C. Chakrabarti, “Multitiered
approach to improving the reliability of multilevel cell PRAM,”
IEEE Workshop on Signal Processing Systems, pp. 114119, 2012.
 K. Sutaria, J. B. Velamala, Y. Cao, “Multilevel
reliability simulation for IC design,” International
Conference on SolidState and Integrated Circuit Technology,
S0703, pp. 14, 2012. [invited]

C. Yang, Y. Emre, Y. Cao, C. Chakrabarti, “Improving
reliability of nonvolatile memory technologies through circuit
level techniques and error control coding,” EURASIP
Journal on Advances in Signal Processing., vol. 2012, no. 211,
pp. 124, October 2012.
 Z. Xu, C. Yang, K. Sutaria, C. Chakrabarti, Y. Cao, “Hierarchical
modeling of phase change memory for reliable design,”
International Conference on Computer Design, pp. 115120, 2012.
 J. B. Velamala, K. Sutaria, H. Shimizu, H. Awano, T. Sato,
Y. Cao, “Statistical aging under dynamic voltage
scaling: a logarithmic model approach,” Custom
Integrated Circuits Conference, 63, pp. 14, 2012. [best
student paper nominee]
 H. Luo, Y. Wang, Y. Cao, Y. Xie, H. Yang, “Temporal
performance degradation under RTN: evaluation and mitigation for
nanoscale circuits," IEEE Computer Society Annual
Symposium on VLSI, pp. 183188, 2012. [best
paper award]
 S. Sinha, G. Yeric, B.
Cline, V. Chandra, Y. Cao, “Design benchmarking to 7nm
with FinFET predictive technology models,”
International Symposium on Low Power Electronics and Design, pp.
1520, 2012.
 S. Sinha, G. Yeric, V. Chandra, B. Cline, Y.
Cao, “Exploring sub20nm FinFET design with predictive
technology models,” Design Automation Conference, pp.
283288, 2012.
 J. Velamala, K. Sutaria, H. Shimuzu, T. Sato,
Y. Cao, “Physics matters: statistical aging prediction
under trapping/detrapping,” Design Automation
Conference, pp. 139144, 2012. [best
paper award nominee]
 J. B. Velamala, K.
B. Sutaria, T. Sato, Y. Cao, “Aging statistics based on
trapping/detrapping: silicon evidence, modeling and longterm
prediction,” International Reliability Physics
Symposium, 2F.2.12F.2.5, 2012.
 S. Gummalla, A. Subramaniam, Y. Cao, C. Chakrabarti, “An
analytical approach to efficient circuit variability analysis in
scaled CMOS design,” International Symposium on Quality
Electronic Design, pp. 641647, 2012.
 A. Subramaniam, R. Singhal, C.C. Wang, Y. Cao, “Leakage
reduction through optimization of regular layout parameters,”
Microelectronics Journal, Elsevier Ltd., vol. 43, no. 1, pp.
2533, January 2012.
2011
 W. Wang, V. Reddy, S. Krishnan, Y. Cao, “Compact
modeling for NBTI and CHC effects,” pp. 4060,
Recent Advancements in Modeling of Semiconductor Processes,
Circuits and ChipLevel Interactions, Edited by Rasit Onur
Topaloglu and Peng Li, Bentham Science Publishers Ltd., 2011.
 Y. Cao,
Predictive Technology Model for Robust Nanoelectronic
Design, Springer, 2011.
 J. Velamala, V. Ravi, Y. Cao, “Failure diagnosis of
asymmetric aging under NBTI,” International Conference
on Computer Aided Design, pp. 428433, 2011.
 S. Sinha, J. Suh, B. Bakkaloglu, Y. Cao, “Workloadaware
neuromorphic design of power controller,” IEEE Journal
on Emerging and Selected Topics in Circuits and Systems, vol. 1,
no. 3, pp. 381390, September 2011.
 H. Luo, Y. Wang, J. Velamala, Y. Cao, Y. Xie, and H. Yang, “The
impact of correlation between NBTI and TDDB on the performance
of digital circuits,” International Midwest Symposium
on Circuits and Systems, pp. 14, 2011. [invited]
 S. Sinha, J. Suh, B. Bakkaloglu, Y. Cao, “A
workloadaware neuromorphic controller for dynamic power and
thermal management,” NASA/ESA Conference on Adaptive
Hardware and Systems, pp. 200207, 2011.
 Y. Ye, F. Liu, M. Chen, S. Nassif, and Y. Cao, “Statistical
modeling and simulation of threshold variation under random
dopant fluctuations and lineedge roughness,” IEEE
Transactions on VLSI Systems, vol. 19, no. 6, pp. 987996, June
2011.
 J. Velamala, R. LiVolsi, M. Torres, Y. Cao, “Design
sensitivity of single event transients in scaled logic circuits,”
Design Automation Conference, pp. 694699, 2011.
 R. Zheng, J. Suh, C. Xu, N. Hakim, B. Bakkaloglu, Y. Cao, “Programmable
analog device array (PANDA): a platform for transistorlevel
analog reconfigurability,” Design Automation
Conference, pp. 322327, 2011.
 E. Mintarno, J. Skaf, R. Zheng, J. Velamala, Y. Cao, S.
Boyd, R. W. Dutton, S. Mitra, “Selftuning for maximized
lifetime energyefficiency in the presence of circuit aging,”
IEEE Transactions on ComputerAided Design of Integrated
Circuits and Systems, vol. 30, no. 5, pp. 760773, May 2011.
 H. Luo, X. Chen, J. Velamala, Y. Wang, Y. Cao, V. Chandra,
Y. Ma, H. Yang, “Circuitlevel delay modeling
considering both TDDB and NBTI,” International
Symposium on Quality Electronic Design, pp. 1421, 2011.
 J. Velamala, C.C. Wang, R. Zheng, Y. Ye, Y. Cao, “Intrinsic
variability and reliability in nanoCMOS,”
Electrochemical Society Transactions, vol. 35, no. 4, pp.
353367, April 2011. [invited]
 S. Sinha, J. Suh, B. Bakkaloglu, Y. Cao, “Workloadaware
lowpower supply voltage controller,” the Neuromorphic
Engineer, 10.2417/1201104.003553, pp. 13, April 2011.
 Y. Wang, X. Chen, W. Wang, Y. Cao, Y. Xie, H. Yang, “Leakage
power and circuit aging cooptimization by gate replacement
techniques,” IEEE Transactions on VLSI Systems, vol.
19, no. 4, pp. 615628, April 2011.
 W. Xu, S. Sinha, H. Wu, M. Dastagir, D. S. Gardner, Y. Cao,
H. Yu, “Sub100 mm scale onchip inductors with CoZrTa
for GHz applications,” Journal of Applied Physics, vol.
109, no. 7, 07A316, pp. 13, April 2011.
 M. Chen, V. Reddy, J. Carulli, S. Krishnan, V. Srinivasan,
V. Rentala, and Y. Cao, “Onthefly measurement of data
path delay degradation in dynamic operations,”
International Reliability Physics Symposium, pp. 3640, 2011.
 R. LiVolsi, K. McCornick, M. Torres, J. Velamala, R. Zheng,
Y. Cao, “Correlation of no trouble found errors to
negative temperature instability,” IEEE Aerospace
Conference, pp. 18, 10.1109/AERO.2011.5747585, 2011.
 W. Xu, S. Sinha, T. Dastagir, H. Wu, B. Bakkaloglu, D. S.
Gardner, Y. Cao, and H. Yu, “Performance enhancement of
onchip inductors with permalloy magnetic rings,” IEEE
Electron Device Letters., vol. 32, no. 1, pp. 6971, January
2011.
2010
 Y. Ye, S. Gummalla, C.C. Wang, C. Chakrabarti, Y. Cao, “Random
variability modeling and its impact on scaled CMOS circuits,”
Journal of Computational Electronics, Springer, vol. 9, pp.
108113, December 2010. [invited]
 Y. Cao, C.C. Wang, Y. Ye, S. Gummalla, C. Chakrabarti, “Intrinsic variability in nanoCMOS design and beyond,” International Electron Devices Meeting,
pp. 414, 2010. [invited]
 W. Xu, S. Sinha, H. Wu, M. Dastagir, D. S. Gardner, Y. Cao, H. Yu, “Sub100µm scale onchip inductors with CoZrTa for GHz applications,”
The 55th Magnetism and Magnetic Materials Conference, 2010.
 Y. Ye, C.C. Wang. C.Y. Chen, Y. Cao, “Simulation of random telegraph noise with 2stage equivalent circuit,” International Conference on Computer Aided Design,
pp. 709713, 2010.
 J. Sun, Y. Cao, J. Wang, “A selfevolving design methodology for power efficient multicore systems,” International Conference on Computer Aided Design,
pp. 264268, 2010.
 C.Y. Chen, C.C. Wang, Y. Ye, Y. Liu, J. SatoIwanaga, A. Inoue, H. Sorada, Y. Cao, R. W. Dutton, “A physicsbased compact model for the 1/f noise in ptype Si/SiGe/Si heterostructure MOSFETs,”
The Workshop on Synthesis and System Integration of Mixed Information Technologies,
R114, 2010.
 T. Dastagir, W. Xu, S. Sinha, H. Wu, Y. Cao, and H. Yu, “Tuning the permeability of permalloy films for onchip inductor applications,” Applied Physics Letters, vol. 97, 162506, pp. 13, October 2010.
 S. Sinha, A. Balijepalli, Y. Cao, “Compact modeling of carbon nanotube transistor and interconnects,” Chapter 12, pp. 217236,
Carbon Nanotubes, Edited by Jose Mauricio Marulanda, INTECH Education and Publishing, 2010.
 W. Wang, V. Reddy, V. Balakrishnan, S. Krishnan, Y. Cao, “Statistical prediction of circuit aging under process variations,” Chapter 5, pp. 101122,
Solid State Circuits Technologies, Edited by Jacobus W. Swart, INTECH Education and Publishing, 2010.
 C.C. Wang, Y. Ye, Y. Cao, “Compact modeling of FeFET and implications on variationinsensitive design,” International Conference on Simulation of Semiconductor Processes and Devices, pp. 247250, 2010.
 S. Sinha, J. Suh, B, Bakkaloglu, Y. Cao, “Workloadaware neuromorphic design of lowpower supply voltage controller,” International Symposium on Low Power Electronics and Design, pp. 241246, 2010.
 J. Lee, C.C. Wang, H. Gashami, L. Bircher, Y. Cao, and N. S. Kim, “Workloadadaptive process tuning strategy for powerefficient multicore processors,” International Symposium on Low Power Electronics and Design, pp. 225230, 2010.
 S. Chellappa, J. Ni, X. Yao, N. Hindman, J. Velamala, M. Chen, Y. Cao, L. T. Clark, “Insitu characterization and extraction of SRAM variability,” Design Automation Conference, pp. 711716, 2010.
 J. B. Velamala, V. Reddy, R. Zheng, S. Krishnan, Y. Cao, “On the bias dependence of time exponent in NBTI and CHC effects,” International Reliability Physics Symposium, pp. 650654, 2010.
 E. Mintarno, R. Zheng, J. Velamala, Y. Cao, S. Boyd, R. W. Dutton, and S. Mitra, “Optimized selftuning to maximize lifetime energyefficiency in the presence of circuit aging,” Design, Automation and Test in Europe, pp. 586591, 2010.
 S. Nassif, N. Mehta, Y. Cao, “A resilience roadmap,” Design, Automation and Test in Europe, pp. 10111016, 2010. [invited]
 R. Singal, A. Balijepalli, A. Subramaniam, C.C. Wang, F. Liu, S. Nassif, Y. Cao, “Modeling and analysis of the nonrectangular gate effect for postlithography circuit simulation,” IEEE Transactions on VLSI Systems, vol. 18, no. 4, pp. 666670, April 2010.
 Y. Cao, F. Liu, “Compact variability modeling in scaled CMOS design,” IEEE Design & Test of Computers, Special Issue on Compact Variability Modeling in Scaled CMOS Design, vol. 27, no. 2, pp. 67, March/April 2010.
 W. Xu, S. Sinha, F. Pan, T. Dastagir, Y. Cao, H. Yu, “Improved frequency response of onchip inductors with patterned magnetic dots,” IEEE Electron Device Letters, vol. 31, no. 3, pp. 207209, March 2010.
 W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, Y. Cao, “The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis,” IEEE Transactions on VLSI Systems, vol. 18, no. 2, pp. 173183, 2010.
 Y. Cao, A. Balijepalli, S. Sinha, C.C. Wang, W. Wang, W. Zhao, “The predictive technology model in the late silicon era and beyond,” Foundations and Trends in Electronic Design Automation, vol. 3, no. 4, pp. 305401, 2010. [invited]
2009
 Y. Cao, J. Tschanz, P. Bose, “Reliability challenges in nanoCMOS design,” IEEE Design & Test of Computers, Special Issue on Design for Reliability at 32nm and Beyond, vol. 26, no. 6, pp. 67, November/December 2009.
 C.C. Wang, W. Zhao, F. Liu, M. Chen, Y. Cao, “Predictive modeling of layoutdependent stress effect in scaled CMOS design,” International Conference on Computer Aided Design, pp. 513520, 2009.
 S. Sinha, W. Xu, J. Velamala, M. Dastagir, B. Bakkaloglu, H. Yu, Y. Cao, “Enabling resonant clock distribution with scaled onchip magnetic inductors,” International Conference on Computer Design, pp. 103108, 2009.
 M. Chen, W. Zhao, F. Liu, Y. Cao, “Finitepoint based transistor model: A new approach to fast circuit simulation,” IEEE Transactions on VLSI Systems, vol. 17, no. 10, pp. 14701480, October 2009.
 S. Sinha, A. Balijepalli, Y. Cao, “Compact model of carbon nanotube transistor and interconnect,” IEEE Transactions on Electron Devices, vol. 56, no. 10, pp. 22322242, October 2009.
 R. Zheng, J. Velamala, V. Reddy, V. Balakrishnan, E. Mintarno, S. Mitra, S. Krishnan, Y. Cao, “Circuit aging prediction for lowpower operation,” Custom Integrated Circuits Conference, pp. 427430, 2009.
 X. Li, W. Zhao, Y. Cao, Z. Zhu, J. Song, D. Bang, C.C. Wang, S. H. Kang, J. Wang, M. Nowak, N. Yu, “Pathfinding for 22nm CMOS designs using predictive technology models,” Custom Integrated Circuits Conference, pp. 227230, 2009.
 C.C. Wang, W. Zhao, M. Chen, Y. Cao, “Compact modeling of stress effects in scaled CMOS,” International Conference on Simulation of Semiconductor Processes and Devices, pp. 14, 2009.
 A. Balijepalli, J. Ervin, W. Lepkowski, Y. Cao, and T. Thornton, “Compact modeling of a PD SOI MESFET for wide temperature designs,” Microelectronics Journal, Elsevier Ltd., vol. 40, no. 9, pp. 12641273, September 2009.
 W. Zhao, X. Li, S. Gu, S. H. Kang, M. Nowak, Y. Cao, “Fieldbased capacitance modeling for sub65nm onchip interconnect,” IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 18621872, September 2009.
 X. Chen, Y. Wang, Y. Cao, Y. Ma, and H. Yang, “Variationaware supply voltage assignment for minimizing circuit aging and leakage,” International Symposium on Low Power Electronics and Design, pp. 3944, 2009. [best paper award nominee]
 Y. Ye, F. Liu, M. Chen, Y. Cao, “Variability analysis under layout patterndependent rapidthermal annealing process,” Design Automation Conference, pp. 551556, 2009.
 T.B. Chan, V. Balakrishnan, Y. Cao, P. Gupta, “Extended burnin for reduced Vth variation,” IEEE International Workshop on Design for Manufacturability and Yield (DFM&Y), pp. 2528, 2009.
 Y. Wang, X. Chen, W. Wang, Y. Cao, Y. Xie, and H. Yang, “Gate replacement techniques for simultaneous leakage and aging optimization,” Design, Automation and Test in Europe, pp. 328333, 2009.
 R. Krishnan, M. Debole, W. Wang, V. Balakrishnan, H. Luo, Y. Wang, Y. Cao, Y. Xie, V. Narayanan, “NewAge: A NBTIestimation framework for microarchitectural components,” International Journal of Parallel Programming., vol. 37, pp. 417431, May 2009.
 Y. Wang, X. Chen, W. Wang, V. Balakrishnan, Y. Cao, Y. Xie, H. Yang, “On the efficacy of input vector control to mitigate circuit aging and leakage,” International Symposium on Quality Electronic Design, pp. 1926, 2009.
 Y. Cao, “What is Predictive Technology Model (PTM)?” ACM/SIGDA ENewsletter, vol. 39, no. 3, March 2009. [invited]
 Y. Ye, F. Liu, Y. Cao, “Modeling of threshold voltage shift under patterndependent RTA process,” SPIE Design for Manufacturability through DesignProcess Integration III, vol. 7275, 72751T19, 2009.
 C.C. Wang, W. Zhao, F. Liu, M. Chen, Y. Cao, “Predictive modeling of layoutdependent stress effect in scaled CMOS design,” International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 2009.
 J. Ni, M. Chen, X. Lin, Y. Cao, “Adaptive transistor model for fast circuit simulation,” International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 2009.
 W. Zhao, F. Liu, K. Agarwal, D. Acharyya, S. R. Nassif, K. Nowka, Y. Cao, “Rigorous extraction of process variations for 65nm CMOS design,” IEEE Transactions on Semiconductor Manufacturing, vol. 22, no. 1, pp. 196203, February 2009.
 M. Debole, R. Krishnan, W. Wang, V. Balakrishnan, H. Luo, Y. Wang, Y. Cao, Y. Xie, V. Narayanan, “NewAge: A framework for NBTI estimation,” Asia and South Pacific Design Automation Conference, pp. 455460, 2009.
2008
 J. M. Wang, Y. Cao, M. Chen, J. Sun, A. Mitev, and K. Potluri, “Capturing device mismatch in analog and mixedsignal designs,” IEEE Circuits and Systems Magazine., vol. 8, no. 4, pp. 3744, 2008. [invited]
 S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, S. Vrudhula, “A scalable model for predicting the effect of NBTI for reliable design,” IET Circuits, Devices & Systems., vol. 2, no. 4, pp. 361371, 2008.
 T. Austin, V. Bertacco, S. Mahlke, Y. Cao, “Reliable systems on unreliable fabrics,” IEEE Design & Test of Computers, vol. 25, no. 4, pp. 322332, February 2008. [invited]
 W. Wang, V. Balakrishnan, B. Yang, Y. Cao, “Statistical prediction of NBTIinduced circuit aging,” International Conference on SolidState and IntegratedCircuit Technology, pp. 416419, 2008. [invited]
 M. Agarwal, V. Balakrishnan, A. Bhuyan, K. Kim, B. C. Paul, Y. Cao, S. Mitra, “Optimized circuit failure prediction for aging: practicality and promise,” International Test Conference, no. 26.1, 2008.
 W. Wang, V. Reddy, B. Yang, V. Balakrishnan, S. Krishnan, Y. Cao, “Statistical prediction of circuit aging under process variations,” Custom Integrated Circuits Conference, pp. 1316, 2008.
 C.C. Wang, W. Zhao, Y. Cao, “Predictive modeling of layoutdependent carrier mobility in stressed CMOS technology,” SRC TECHNON, 2008.
 V. Balakrishnan, W. Wang, Y. Cao, “Statistical prediction of circuit aging under process and design uncertainties,” SRC TECHNON, 2008.
 Y. Ye, F. Liu, S. Nassif, Y. Cao, “Statistical modeling and simulation of threshold variation under dopant fluctuations and lineedge roughness,” Design Automation Conference, pp. 900905, 2008.
 S. Sinha, A. Balijepalli, Y. Cao, “A simplified model of carbon nanotube transistor with applications to analog and digital design,” International Symposium on Quality Electronic Design, pp. 502507, 2008.
 W. Wang, S. Yang, and Y. Cao, “Node criticality computation for circuit timing analysis and optimization under NBTI effect,” International Symposium on Quality Electronic Design, pp. 763768, 2008.
 X. Li, Y. Cao, “Projectionbased piecewiselinear response surface modeling for strongly nonlinear VLSI performance variations,” International Symposium on Quality Electronic Design, pp. 108113, 2008.
 D. Ganesan, A. Mitev, J. Wang, Y. Cao, “Finitepoint gate model for fast timing and power analysis,” International Symposium on Quality Electronic Design, pp. 657662, 2008.
 L. Cheng, Y. Lin, L. He, and Y. Cao, “Tracebased framework for concurrent development of process and FPGA architecture considering process variation and reliability,” International Symposium on FieldProgrammable Gate Arrays, pp. 159168, 2008.
 M. Agarwal, V. Balakrishnan, A. Bhuyan, K. Kim, M. Mizuno, B. C. Paul, Y. Cao, S. Mitra, "Optimized circuit fialure prediction for aging: practicality and promise," International Workshop on Timing Issues in teh Spcification and Synthesis of Digital System (TAU), 2008.
 B. H. Calhoun, Y. Cao, X. Li, K. Mai, L. T. Pileggi, R. A. Rutenbar, and K. L. Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS,” Proceedings of the IEEE, vol. 96, no. 2, pp. 343365, February 2008. [invited]
 A. Subramaniam, R. Singhal, C.C. Wang, Y. Cao, “Design rule optimization of regular layout for leakage reduction in nanoscale design,” Asia and South Pacific Design Automation Conference, pp. 474479, 2008.
2007
 W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda, S. Krishnan, Y. Cao, “Compact modeling and simulation of circuit reliability for 65nm CMOS technology,” IEEE Transactions on Device and Materials Reliability, vol. 7, no. 4, pp. 509517, December 2007. [invited]
 Y. Cao and L. T. Clark, “Mapping statistical process variations toward circuit performance variability: an analytical modeling approach,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol. 26, no. 10, pp. 18661873, October 2007.
 W. Zhao and Y. Cao, “Predictive technology model for nanoCMOS design exploration,” ACM Journal on Emerging Technologies in Computing Systems, vol. 3, no. 1, pp. 117, April 2007.
 W. Zhao, X. Li, M. Nowak, and Y. Cao, "Predictive technology modeling for 32nm low power design," to be published at International Semiconductor Device Research Symposium, 2007.
 W. Wang, Z. Wei, S. Yang, Y. Cao, “An efficient method to identify critical gates under circuit aging,” International Conference on Computer Aided Design, pp. 735740, 2007.
 D. Ganesan, D. Shanmugasundaram, A. Mitev, Y. Cao, J. Wang, “A robust finitepoint based gate model considering process variations,” International Conference on Computer Aided Design, pp. 692697, 2007.
 Y. Cao, C. C. McAndrew, “MOSFET modeling for 45nm and beyond,” embedded tutorial, International Conference on Computer Aided Design, pp. 638643, 2007. [invited]
 W. Wang, V. Reddy, A. T. Krishnan, S. Krishnan, Y. Cao, “An integrated modeling paradigm of circuit reliability for 65nm CMOS technology,” Custom Integrated Circuits Conference, pp. 511514, 2007.
 W. Zhao, F. Liu, K. Agarwal, D. Acharyya, S. Nassif, K. Nowka, Y. Cao, “Rigorous extraction of process variations for 65nm CMOS design,” European SolidState Circuits Conference, pp. 8992, 2007.
 W. Wang, V. Reddy, A. T. Krishnan, S. Krishnan, Y. Cao, “An integrated modeling paradigm of circuit reliability for 65nm CMOS technology,” SRC TECHNON, 2007.
 A. Balijepalli, S. Sinha, Y. Cao, “Compact modeling of carbon nanotube transistor for early stage processdesign exploration,” International Symposium on Low Power Electronics and Design, pp. 27, 2007. [best paper award]
 W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, F. Liu, S. Vrudhula, Y. Cao, “The impact of NBTI on the performance of combinational and sequential circuits,” Design Automation Conference, pp. 364369, 2007. [PDF]
 R. Singhal, A. Balijepalli, A. Subramaniam, F. Liu, S. Nassif, Y. Cao, “Modeling and analysis of nonrectangular gate for postlithography circuit simulation,” Design Automation Conference, pp. 823828, 2007.
 M. Chen, W. Zhao, F. Liu, Y. Cao, “Fast statistical circuit analysis with finitepoint based transistor model,” Design, Automation and Test in Europe, pp. 13911396, 2007.
 A. Balijepalli, J. Ervin, Y. Cao, and T. Thornton, “Compact modeling of a PD SOI MESFET for widetemperature designs,” International Symposium on Quality Electronic Design, pp. 133138, 2007.
 R. Vattikonda, Y. Luo, A. Gyure, X. Qi, S. Lo, M. Shahram, Y. Cao, K. Singhal, and D. Toffolon, “A new simulation method for NBTI analysis in SPICE environment,” International Symposium on Quality Electronic Design, pp. 4146, 2007.
 T. Sairam, W. Zhao, Y. Cao, “Optimizing FinFET technology for highspeed and lowpower design,” Great Lakes Symposium on VLSI, pp. 7377, 2007. [best paper award nominee]
2006
 H. Qin, R. Vattikonda, T. Trinh, Y. Cao, J. Rabaey, “SRAM cell optimization for ultralow power standby,” ASP Journal of Low Power Electronics, vol. 2, no. 3, pp. 401411, December 2006.
 W. Zhao, Y. Cao, “New generation of predictive technology model for sub45nm early design exploration,” IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 28162823, November 2006.
 J. He, M. Fang, B. Li, G. Zhang, Y. Cao, “A new analytic approximation to general diode equation,” Elsevier SolidState Electronics, vol. 50, no. 9, pp. 13711374, September 2006.
 S. Bhardwaj, Y. Cao, S. Vrudhula, “Statistical leakage minimization of digital circuits using gate sizing, gate length biasing, and threshold voltage selection,” ASP Journal of Low Power Electronics, vol. 2, no. 2, pp. 240250, August 2006.
 B. T. Cline, K. Chopra, D. Blaauw, and Y. Cao “Analysis and modeling of CD variation for statistical static timing,” International Conference on Computer Aided Design, pp. 6066, 2006.
 Y. Cao, W. Zhao, “Predictive technology model for nanoCMOS design exploration,” International Conference on NanoNetworks, 2006. [invited]
 S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, S. Vrudhula, “Predictive modeling of the NBTI effect for reliable design,” Custom Integrated Circuits Conference, pp. 189192, 2006.
 R. Vattikonda, W. Wang, Y. Cao, “Modeling and minimization of PMOS NBTI effect for robust nanometer design,” Design Automation Conference, pp. 10471052, 2006.
 S. Bhardwaj, S. Vrudhula, Praveen Ghanta, Y. Cao, “Modeling of intradie process variations for accurate analysis and optimization of nanoscale circuits,” Design Automation Conference, pp. 791796, 2006.
 A. Balijepalli, J. Ervin, P. Joshi, J. Yang, Y. Cao, and T. J. Thornton, “Highvoltage CMOS compatible SOI MESFET characterization and SPICE model extraction,” IEEE International Microwave Symposium, pp. 13351338, 2006.
 S. Bhardwaj, S. Vrudhula, and Y. Cao, “LOTUS: leakage optimization under timing uncertainty for standardcell designs,” International Symposium on Quality electronic Design, pp. 717722, 2006.
 W. Zhao and Y. Cao, “New generation of predictive technology model for sub45nm design exploration,” International Symposium on Quality Electronic Design, pp. 585590, 2006. [best paper award nominee]
 M. Chen and Y. Cao, “Analysis of pulse signaling for lowpower onchip global bus design,” International Symposium on Quality electronic Design, pp. 401406, 2006.
 S. Bhardwaj, Y. Cao, and S. Vrudhula, “Statistical leakage minimization using gate sizing, gate length biasing and threshold voltage selection,” Asia and South Pacific Design Automation Conference, pp. 953958, 2006. [best paper award nominee]
2005
 J. Chen, L. T. Clark, and Y. Cao, “Maximum FanIn/Out: Ultralow voltage circuit design in the presence of variations,” IEEE Circuits and Devices Magazine, vol. 21, no. 6, pp. 1220, November 2005.
 Y. Cao, X.D. Yang, X. Huang, and D. Sylvester, "Switchfactor based loop RLC modeling for efficient timing analysis," IEEE Transactions on VLSI Systems, vol. 13, no. 9, pp. 10721078, September 2005.
 H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. M. Rabaey, "Standby supply voltage minimization for deep submicron SRAM," Elsevier Microelectronics Journal, vol. 36, no. 9, pp. 789800, September 2005.
 Y. Cao, X. Huang, D. Sylvester, T.J. King, and C. Hu, "Impact of onchip interconnect frequencydependent R(f)L(f) on digital and RF design," IEEE Transactions on VLSI Systems, vol. 13, no. 1, pp. 158162, January 2005.
 J. Chen, L. T. Clark, Y. Cao, “Robust subthreshold design of high fanin/out circuits,” International Conference on Computer Design, pp. 405410, 2005.
 Y. Cao and L. T. Clark, “Mapping statistical process variations toward circuit performance variability: an analytical modeling approach,” Design Automation Conference, pp. 658663, 2005.
 P. Friedberg, Y. Cao, J. Cain, R. Wang, J. Rabaey, and C. Spanos, “Modeling withindie spatial correlation effects for processdesign cooptimization,” Microlithography Program, SPIE, 2005.
 P. Friedberg, Y. Cao, J. Cain, R. Wang, J. Rabaey, and C. Spanos, “Modeling withindie spatial correlation effects for processdesign cooptimization,” International Symposium on Quality Electronic Design, pp. 516521, 2005.




