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It is widely recognized that
process variation is emerging as a fundamental challenge to IC design in
scaled CMOS technology; and it will have profound impact on nearly all
aspects of circuit performance. While some of the negative effects of
variability can be handled with improvements in the manufacturing process,
the industry is starting to accept the fact that some of the effects are
better mitigated during the design process. Handling variability in the
design process will require accurate and appropriate models of variability
and its dependence on designable parameters (i.e. layout), and its spatial
and temporal distributions. It also requires carefully designed test
structures and proper statistical data analysis methods to extract
meaningful models from large volumes of silicon measurements. The resulting
compact modeling of systematic, random, spatial, and temporal variations is
essential to abstract the physical level variations into a format the
designers (and more importantly, the tools they use) can utilize. This
workshop provides a forum to discuss current practice as well as near
future research needs in test structure design, variability
characterization, compact variability modeling, and statistical simulation.
Key Topics
 Physics mechanisms and
technology trends of device-level variations
First-principles
simulation methods for predicting variability
Time-dependent variation
and their interaction with other variation sources
Compact modeling of
variations in devices and interconnect
Device and circuit level modeling
techniques
Test structure design for
variability
Variability
characterization, bounding and extraction
Statistical data analysis
and model extraction methods
Novel implementation and
simulation techniques for dealing with variability
Tentative Agenda
9:00 – 9:10am Opening Remarks
9:10 – 9:50am Keynote:
Rob Aitken (ARM): Knowns and Unknowns in Variability Modeling
9:50 – 10:30am Takayasu
Sakurai (Univ. of Tokyo): Deep-volt
Design under Variability
10:30 – 11:00am Morning Break/Discussion
11:00 – 11:40am Vijay Reddy (TI): An Overview of Circuit Aging in SOCs
11:40 – 12:20pm Gilson Wirth (UFRGS):
Charge Trapping Phenomena in MOSFETs: From Noise to Bias Temperature Instability
12:20 – 1:30pm Lunch
1:30 – 2:10pm Keynote:
Luigi Capodieci (GF): DFM Methodologies for Effective Variability
Management in Physical Design at 20nm and Beyond
2:10 – 2:50pm Kiyoshi Takeuchi (Renesas): Impact
of Random Telegraph Noise on Circuit Reliability
2:50 – 3:30pm Poster Presentation
3:30 – 4:00pm Afternoon Break/Discussion
4:00 – 5:00pm Poster Session
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