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Research
My research focuses on
modeling and design techniques for reliable, low-power, and
high-performance systems, motivated by both evolutionary and revolutionary
advances in nanoscale technology. If you are
interested, welcome to come by during my office hours. For more in-depth
information, please visit the webpage of the NIMO Group.
I am
particularly interested in the following topics:
 Compact modeling for nanoscale CMOS and
post-silicon technologies
Physical-level design and tools for variability
and reliability
Reconfigurable design of CMOS circuits and beyond
Reliable integration of emerging technologies
High-speed and low-power design techniques
To
explore early stage design solutions, Predictive
Technology Model (PTM) is developed for sub-45nm technology
generations, covering traditional bulk CMOS, alternative materials and
structures (e.g., FinFET), and post-silicon devices (e.g., CNT-FET). In
addition, this predictive modeling framework accurately captures emerging
physical effects, such as variability and reliability. To investigate more,
welcome to visit PTM and send me your
valuable feedbacks.
Teaching
EEE
425 (F12), “Digital systems and circuits,”
Office hours: T/Th, 1:30-2:30pm
EEE
425 (F11), “Digital systems and circuits,”
Office hours: W/Th, 1:00-2:00pm
EEE
525 (S11), “VLSI design,” Office hours: M/W, 11:30am-12:30pm
EEE 425 (F10),
“Digital systems and circuits,” Office hours:
W/Th, 1:00-2:00pm
EEE 525 (S10),
“VLSI design,” Office hours: W, 1:00-3:00pm
EEE
425 (F09), “Digital systems and circuits,” Office hours: T/Th, 1:00-2:00pm
EEE 598 (S09), “Modeling and Design Solutions for Nano-CMOS
Technology,” Office hours: T/Th,
10:30-11:30am
EEE 333
(F08), “HDL and Programmable Logic”, Office hours: T/Th, 3:00-4:00pm
EEE 333
(S08), “HDL and Programmable Logic”, Office hours: T/Th, 11:00-12:00pm
EEE 525
(F07), “VLSI design,” Office hours: M/W, 2:00-3:00pm
EEE 525
(S07), “VLSI design,” Office hours: M/W, 1:30-2:30pm
EEE 598
(F06), “Modeling and Design for Nano-CMOS Technology,” Office hours: M/W, 1:30-2:30pm
EEE 525
(S06), “VLSI design,” Office hours: M/W, 1:30-2:30pm.
EEE 425
(F05), “Digital systems and circuits,” Office hours: M/W, 1:40-3:00pm.
EEE 525
(S05), “VLSI design,” Office hours: T, 3-5pm; Th, 2-3pm.
Professional
Activities
Chair, Circuit Reliability Committee, IEEE
International Reliability Physics Symposium, 2013.
Associate Editor, IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, 2012 – present.
Co-organizer, Tutorial on CMOS Reliability,
DATE, 2011.
Chair, Signal Integrity and Reliability
Sub-Committee, Design Automation Conference, 2010.
Associate Editor, Journal of Computational Electronics,
Springer, 2010 – present.
Program Chair, 1st IEEE CASS Summer
School on Physical Design of Reliable Systems, Brazil, 2010.
Chair, Circuit Reliability Committee, IEEE
International Reliability Physics Symposium, 2010.
Guest Editor, IEEE Design & Test of
Computers, 2009/2010.
Chair, VLSI Circuit and Architecture Track,
ISVLSI, 2009.
Organizer, Tutorial on Circuit Reliability,
ASP-DAC, 2009.
Vice-chair, Circuit Reliability Committee, IRPS,
2009.
Co-organizer, IEEE/ACM Workshop on Variability
Modeling and Characterization (VMC), 2008 - present.
Chair, Device Modeling and Simulation
Subcommittee, ICCAD, 2008.
Design Contest Chair, ISLPED 2008/2009.
Member of the Compact Modeling Technical
Committee, IEEE Electron Devices Society, 2007 - present
Program Committee Member: CICC 2012-2013,
DAC 2007-2010, DRV 2009, GLSVLSI 2006-2010, ICCAD 2005-2008, ICCD 2005-2007,
IEDM 2011-2012, IOLTS 2009-2011, IRPS 2009-2011, ISLPED 2005-2009, ISQED
2008, ISVLSI 2009, SLIP 2007-2011.
Session
Chair: DAC 2005/2007/2009, ICCAD 2005/2006, ICCD 2005, IEDM 2012, IRPS
2010, ISLPED 2005/2007, ISQED 2006.
Honors
Best
Paper Award: “Temporal performance degradation under RTN: evaluation and
mitigation for nanoscale circuits,” ISVLSI 2012.
Top 5%
Teaching Award, Ira. A. Fulton Schools of Engineering, ASU, 2012.
Chunhui
Award for Outstanding Oversea Chinese Scholars, Ministry of Education of
China, 2011.
Top 5%
Teaching Award, Ira. A. Fulton Schools of Engineering, ASU, 2010.
ACM
SIGDA Outstanding New Faculty Award, 2009.
Promotion
and Tenure Faculty Exemplar, Arizona State University, 2009.
IEEE
Distinguished Lecturer of the Circuits and Systems Society (CAS), 2009.
Chunhui
Award for Outstanding Oversea Chinese Scholars, Ministry of Education of
China, 2008.
Best
Paper Award: “Compact modeling of carbon nanotube transistor for early
stage process-design exploration,” ISLPED 2007.
IBM
Faculty Award, 2007.
NSF
Faculty Early Career Development (CAREER) Award, 2006.
IBM
Faculty Award, 2006.
Best
Paper Award: “SRAM leakage suppression by minimizing standby supply
voltage,” ISQED 2004.
Beatrice Winner Award: “Accurate in-situ
measurement of peak noise and signal delay induced by interconnect
coupling,” ISSCC 2000.
Regents Fellowship, University of California,
Santa Cruz, 1996.
Publications
Some of
my recent publications are selected as follows. A full list is available here.
- Y. Cao, Predictive Technology Model for Robust
Nanoelectronic Design, Springer, 2011 (http://dx.doi.org/10.1007/978-1-4614-0445-3).
- B. Wong, A. Mittal, Y. Cao, and G. Starr, Nano-CMOS
Circuit and Physical Design, John Wiley & Sons, Inc., 2004.
- Y. Ye, F. Liu, M. Chen,
S. Nassif, and Y. Cao, “Statistical modeling and simulation of
threshold variation under random dopant fluctuations and line-edge
roughness,” IEEE Transactions on
VLSI Systems, vol. 19, no. 6, pp. 987-996, June 2011.
- W. Wang, S. Yang, S.
Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, Y. Cao, “The impact of
NBTI effect on combinational circuit: modeling, simulation, and
analysis,” IEEE Transactions on
VLSI Systems, vol. 18, no. 2, pp. 173-183, 2010.
- S. Chellappa, J. Ni, X. Yao, N. Hindman, J.
Velamala, M. Chen, Y. Cao, L. T. Clark, “In-situ characterization and
extraction of SRAM variability,” Design
Automation Conference, pp. 711-716, 2010.
- C.-C. Wang, W. Zhao, F. Liu, M. Chen, Y. Cao,
“Predictive modeling of layout-dependent stress effect in scaled CMOS
design,” International
Conference on Computer Aided Design, pp. 513-520, 2009.
- S. Sinha, A. Balijepalli, Y. Cao, “Compact model
of carbon nanotube transistor and interconnect,” IEEE Transactions on Electron Devices, vol. 56, no. 10,
pp. 2232-2242, October 2009.
- W. Zhao, X. Li, S. Gu, S. H. Kang, M. Nowak, Y.
Cao, “Field-based capacitance modeling for sub-65nm on-chip
interconnect,” IEEE Transactions
on Electron Devices, vol. 56, no. 9, pp. 1862-1872, September
2009.
- Y. Ye, F. Liu, M. Chen, Y. Cao, “Variability
analysis under layout pattern-dependent rapid-thermal annealing
process,” Design Automation
Conference, pp. 551-556, 2009.
- W. Zhao, F. Liu, K.
Agarwal, D. Acharyya, S. R. Nassif, K. Nowka, Y. Cao, “Rigorous
extraction of process variations for 65nm CMOS design,”IEEE
Transactions on Semiconductor Manufacturing, vol. 22, no. 1, pp.
196-203, February 2009.
- B. H. Calhoun, Y. Cao, X. Li, K. Mai, L. T.
Pileggi, R. A. Rutenbar, and K. L. Shepard, "Digital circuit
design challenges and opportunities in the era of nanoscale
CMOS," Proceedings of IEEE, vol. 96, no. 2, pp. 343-365, February
2008.
- W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda,
S. Krishnan, Y. Cao, “Compact modeling and simulation of circuit
reliability for 65nm CMOS technology”, IEEE Transactions on Device
and Materials Reliability, vol. 7, no. 4, pp. 509-517, December
2007.
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