Yu (Kevin) Cao

Professor, School of ECEE

Affiliated Professor, Computer Science and Engineering

Arizona State University

Ph.D. in EECS, University of California, Berkeley, 2002

B.S. in Physics, Peking University, 1996

Curriculum Vitae

Nanoscale Integration and Modeling Group (NIMO)

Contact

ISTB4 563, 781 E. Terrace Road, ASU, Tempe, AZ 85287-5804

Tel.: 480-965-1472; FAX: 480-727-9209

E-mail: ycao at asu dot edu

Research

My research focuses on modeling and design techniques for reliable, low-power, and high-performance systems, motivated by advances in nanoelectronics and information analytics. If you are interested, welcome to come by during my office hours. For more in-depth information, please visit the webpage of the NIMO Group.

I am particularly interested in the following topics:

  Neural-inspired design for learning on-a-chip

  Physical-level design and tools for integrated systems

  Compact modeling for nanoscale CMOS and post-silicon technologies

  Reconfigurable design of CMOS circuits and beyond

Teaching

EEE 425 (F16), “Digital systems and circuits,” Office hours: T/Th, 11:00am-12:00pm

EEE 598 (S16), “VLSI design for reliability,” Office hours: Th, 1:30-2:30pm

EEE 425 (S16, on line), “Digital systems and circuits,” Office hours: Th, 3:00-4:00pm

EEE 425 (F15), “Digital systems and circuits,” Office hours: M/W, 1:00-2:00pm

EEE 598 (S15), “VLSI design for reliability,” Office hours: M/W, 3:00-4:00pm

EEE 425 (F14), “Digital systems and circuits,” Office hours: M/W, 1:30-2:30pm

Kyoto University (F13), “Perspectives in informatics 3,” Office hours: T, 1:30-2:30pm

EEE 425 (F12), “Digital systems and circuits,” Office hours: T/Th, 1:30-2:30pm

EEE 425 (F11), “Digital systems and circuits,” Office hours: W/Th, 1:00-2:00pm

EEE 525 (S11), “VLSI design,” Office hours: M/W, 11:30am-12:30pm

EEE 425 (F10), “Digital systems and circuits,” Office hours: W/Th, 1:00-2:00pm

EEE 525 (S10), “VLSI design,” Office hours: W, 1:00-3:00pm

EEE 425 (F09), “Digital systems and circuits,” Office hours: T/Th, 1:00-2:00pm

EEE 598 (S09), Modeling and Design Solutions for Nano-CMOS Technology, Office hours: T/Th, 10:30-11:30am

EEE 333 (F08), “HDL and Programmable Logic”, Office hours: T/Th, 3:00-4:00pm

EEE 333 (S08), “HDL and Programmable Logic”, Office hours: T/Th, 11:00-12:00pm

EEE 525 (F07), “VLSI design,” Office hours: M/W, 2:00-3:00pm

EEE 525 (S07), “VLSI design,” Office hours: M/W, 1:30-2:30pm

EEE 598 (F06), “Modeling and Design for Nano-CMOS Technology,” Office hours: M/W, 1:30-2:30pm

EEE 525 (S06), “VLSI design,” Office hours: M/W, 1:30-2:30pm.

EEE 425 (F05), “Digital systems and circuits,” Office hours: M/W, 1:40-3:00pm.

EEE 525 (S05), “VLSI design,” Office hours: T, 3-5pm; Th, 2-3pm.

Professional Activities

Guest Editor, ACM Journal on Emerging Technologies in Computing Systems, Special Issue on Hardware and Algorithms for Learning On-a-chip, 2016

Guest Editor, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Special Issue on Cross-layer Reliability and Security, 2016

Guest Editor, IEEE Transactions on Nanotechnology, Special Issue on Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing, 2016

Advisory Board Member, International Membrane Computing Society (IMCS), 2016

Chair, Digital Design, Timing and Simulation Sub-Committee, Design Automation Conference (DAC), 2016, 2017

Chair, Circuit Reliability Committee, IEEE International Reliability Physics Symposium (IRPS), 2016

Chair of Workshop on Hardware and Algorithms for Learning On-a-chip (HALO), 2015, 2016

Chair of Workshop on Adaptive Learning On-a-chip: Hardware and Algorithms (ALOHA) at SIAM International Conference on Data Mining, 2015.

Co-organizer, Special Session on Cross-layer Technology and Design Solutions for Resilience, IEEE International Symposium on Circuits and Systems (ISCAS), 2015

Chair, Simulation and Modeling Committee, IEEE Custom Integrated Circuits Conference (CICC), 2014

Co-chair, Circuit Aging/Simulation and Circuit Reliability Committee, IEEE International Reliability Physics Symposium (IRPS), 2014

Co-organizer, Special Session on Neuron Inspired Computing using Nanotechnology, Asia and South Pacific Design Automation Conference (ASP-DAC), 2014

Co-chair, Simulation and Modeling Committee, IEEE Custom Integrated Circuits Conference (CICC), 2013

Chair, Circuit Reliability Committee, IEEE International Reliability Physics Symposium, 2013.

Associate Editor, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012 – present.

Co-organizer, Tutorial on CMOS Reliability, DATE, 2011.

Chair, Signal Integrity and Reliability Sub-Committee, Design Automation Conference, 2010.

Associate Editor, Journal of Computational Electronics, Springer, 2010 – 2013.

Program Chair, 1st IEEE CASS Summer School on Physical Design of Reliable Systems, Brazil, 2010.

Chair, Circuit Reliability Committee, IEEE International Reliability Physics Symposium, 2010.

Guest Editor, IEEE Design & Test of Computers, 2009/2010.

Chair, VLSI Circuit and Architecture Track, ISVLSI, 2009.

Organizer, Tutorial on Circuit Reliability, ASP-DAC, 2009.

Vice-chair, Circuit Reliability Committee, IRPS, 2009.

Co-organizer, IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), 2008 - present.

Chair, Device Modeling and Simulation Subcommittee, ICCAD, 2008.

Design Contest Chair, ISLPED 2008/2009.

Member of the Compact Modeling Technical Committee, IEEE Electron Devices Society, 2007 - present

Program Committee Member:  CICC 2012-2014, DAC 2007-2010, DRV 2009, GLSVLSI 2006-2010, ICCAD 2005-2008, ICCD 2005-2007, ICMTS 2014, ICSICT 2014, IEDM 2011-2012, IOLTS 2009-2011/2013, IRPS 2009-2014, ISLPED 2005-2009/2013-2014, ISQED 2008, ISVLSI 2009, IWCM 2012-2014 NANOARCH 2016, SLIP 2007-2011.

Session Chair: ASP-DAC 2014, CICC 2012/2013, DAC 2005/2007/2009/2013, ICCAD 2005/2006, ICCD 2005, IEDM 2012, IRPS 2010/2013, ISLPED 2005/2007, ISQED 2006, SLIP 2010.

Honors

IEEE Fellow, “for development of predictive technology models for reliable circuit and system integration,” 2017.

Top 5% Teaching Award, Ira. A. Fulton Schools of Engineering, ASU, 2016.

Top 5% Teaching Award, Ira. A. Fulton Schools of Engineering, ASU, 2015.

Top 5% Teaching Award, Ira. A. Fulton Schools of Engineering, ASU, 2013.

Best Paper Award: “Temporal performance degradation under RTN: evaluation and mitigation for nanoscale circuits,” ISVLSI 2012.

Top 5% Teaching Award, Ira. A. Fulton Schools of Engineering, ASU, 2012.

Top 5% Teaching Award, Ira. A. Fulton Schools of Engineering, ASU, 2010.

ACM SIGDA Outstanding New Faculty Award, 2009.

Promotion and Tenure Faculty Exemplar, Arizona State University, 2009.

IEEE Distinguished Lecturer of the Circuits and Systems Society (CAS), 2009.

Chunhui Award for Outstanding Oversea Chinese Scholars, Ministry of Education of China, 2008.

Best Paper Award: “Compact modeling of carbon nanotube transistor for early stage process-design exploration,” ISLPED 2007.

IBM Faculty Award, 2007.

NSF Faculty Early Career Development (CAREER) Award, 2006.

IBM Faculty Award, 2006.

Best Paper Award: “SRAM leakage suppression by minimizing standby supply voltage,” ISQED 2004.

Beatrice Winner Award: “Accurate in-situ measurement of peak noise and signal delay induced by interconnect coupling,” ISSCC 2000.

Regents Fellowship, University of California, Santa Cruz, 1996.

Publications

Some of my publications are selected as follows. A full list is available here.

  • Y. Cao, Predictive Technology Model for Robust Nanoelectronic Design, Springer, 2011 (http://dx.doi.org/10.1007/978-1-4614-0445-3).
  • B. Wong, A. Mittal, Y. Cao, and G. Starr, Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., 2004.
  • Y. Ma, N. Suda, J. Seo, Y. Cao, S. Vrudhula, “Scalable and modularized RTL compilation of convolutional neural networks onto FPGA,” International Conference on Field-Programmable Logic and Applications, S5b.1-8, 2016
  • J. Seo, B. Lin, M. Kim, P.-Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, S. Vrudhula, S. Yu, J. Ye, Y. Cao, “On-chip sparse learning acceleration with CMOS and resistive synaptic devices,” IEEE Transactions on Nanotechnology, Special Issue on Cognitive and Natural Computing with Nanotechnology, vol. 14, no. 6, pp. 969-979, November 2015.
  • K. B. Sutaria, A. Mohanty, R. Wang, R. Huang, Y. Cao, “Accelerated aging in analog and digital circuits with feedback,” IEEE Transactions on Device and Materials Reliability, vol. 15, no. 3, pp. 384-393, September 2015. 
  • Y. Cao, J. Velamala, K. Sutaria, M. S.-W. Chen, J. Ahlbin, I. S. Esqueda, M. Bajura, M. Fritze, “Cross-layer modeling and simulation of circuit reliability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 1, pp. 8-23, January 2014. [Keynote]
  • J. B. Velamala, K. B. Sutaria, H. Shimuzu, H. Awano, T. Sato, G. Wirth, Y. Cao, “Compact modeling of statistical BTI under trapping/detrapping,” IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3645-3654, November 2013.

 

Last updated on December 10, 2016. Contents subject to change. All rights reserved.