Workshop on Chiplet-based Heterogeneous Integration and CO-design
July 9, 2023
Moscone Center
San Francisco, CA
Contemporary microelectronic design is facing tremendous challenges in memory bandwidth, processing speed and power consumption. Although recent advances in monolithic design (e.g. near-memory and in-memory computing) help relieve some issues, the scaling trend is still lagging behind the ever increasing demand of AI, HPC and other applications.
In this context, technological innovations beyond a monolithic chip, such as 2.5D and 3D packaging at the macro and micro levels, are critical to enabling heterogeneous integration with various types of chiplets, and bringing significant performance and cost benefits for future systems. Such a paradigm shift further drives new innovations on chiplet IPs, heterogeneous architectures and system mapping.
This workshop is designed to be a forum that is highly interactive, timely and informative, on the related topics:
- Roadmap and technology perspectives of heterogeneous integration
- IP definition of chiplets
- Signaling interface cross chiplets
- Network topology for data movement
- Design solutions for power delivery
- Thermal management
- High-level synthesis for the chiplet system
- Architectural innovations
- Ecocystems of IPs and EDA tools
Tentative Program
Time | Activity |
---|---|
8:15am – 8:30am | Introduction and opening remarks |
8:30am – 11:00am | Session 1: Chiplet-based 2.5D/3D System Madhavan Swaminathan (Pennsylvania State University): Heterogeneous Integration – A 10 Year & Beyond Roadmap: Design Space Exploration, Co-Design & Optimization for Future Chiplet Systems Rangharajan Venkatesan (NVidia): Flexible Performance Scaling with Multi-Chip-Modules Deepak Kulkarni (AMD): Heterogeneous Integration with Chiplets Paul Fahey (SK Hynix): From 2.5D to 3D, Learnings from HBM SIP Technology Farah Fahim (Fermi Lab): Co-designed Chiplets for 3D Integration: Advanced Scientific Instrumentation |
11:00am – 11:30am | Panel Discussion |
11:30am – 1:30pm | Lunch |
1:30pm – 4:30pm | Session 2: Ecosystem for Chiplet-based Integration Sung-kyu Lim (DARPA): Fine-Grained Physical Design Automation for Densely Digital 3D ICs John Damoulakis (Cadence): Speeding-up 3DIC Technology – The E Rob Aitken (Synopsys): Ecosystem for Chiplet-based Systems Anthony Mastroianni (Siemens): Heterogeneous Design Methods Arindam Mallik (IMEC): Addressing the Innovator’s Dilemma in an Increasingly Expensive World Syrus Ziai (Eliyan): Developing Efficient Chiplets for High Performance Applications |
4:30pm – 5:00pm | Panel Discussion |
Organizers
Yu (Kevin) Cao, Arizona State University
Puneet Gupta, University of California, Los Angeles
Frank Liu, Oak Ridge National Lab